International Business Machines Corporation

Marvell Asia Pte., Ltd.

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Deepak I Hanagandi

Michael Richard Ouellette

Aravindan J Busi

Krishnendu Mondal

Michael Anthony Ziegerhofer

Kiran K Narayan

Kevin William Gorman

Igor Arsovski

Venkatraghavan Bringivijayaraghavan

Valerie Hornbeck Chickanosky

Kalpesh R Lodha

Disclosed is a processing unit for computing a convolution of an activations matrix (e.g., a N&#xd7;N activations matrix) and a weights kernel (e.g., a M&#xd7;M weights kernel). The processing unit specifically employs an array of processing elements and a hardware-implemented spiral algorithm to compute the convolution. Due to this spiral algorithm, the need for a discrete data setup logic block is avoided, activation values from the activations matrix can be pre-loaded into processing elements only one time so that the need to repeatedly access the activations matrix is avoided, and the computation can be completed in a relatively low number of clock cycles, which is independent of the number of activation values in the activation matrix and which is equal to the number of weight values in a weights kernel. Also disclosed is an associated processing method.

Processing unit and method for computing a convolution using a hardware-implemented spiral algorithm

A memory architecture and a processing unit that incorporates the memory architecture and a systolic array. The memory architecture includes: memory array(s) with multi-port (MP) memory cells; first wordlines connected to the cells in each row; and, depending upon the embodiment, second wordlines connected to diagonals of cells or diagonals of sets of cells. Data from a data input matrix is written to the memory cells during first port write operations using the first wordlines and read out from the memory cells during second port read operations using the second wordlines. Due to the diagonal orientation of the second wordlines and due to additional features (e.g., additional rows of memory cells that store static zero data values or read data mask generators that generate read data masks), data read from the memory architecture and input directly into a systolic array is in the proper order, as specified by a data setup matrix.

Multi-port memory architecture for a systolic array

The present disclosure relates to a structure including a memory built-in self test (MBIST) circuit which is configured to repair a multi-cell failure for a plurality of patterns in a single wordline of a sliding window of a memory.

Memory built-in self test error correcting code (MBIST ECC) for low voltage memories

A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.

Arbitration for memory diagnostics

Approaches for a memory built-in self-test (MBIST) are provided. The MBIST circuit includes a fail status register which receives a new fail signal value in response to a detection of a unique fail in a pattern, and a pattern mask register which stores at an end of the pattern a different value of the new fail signal value representative of the unique fail.

Memory built-in self-test (MBIST) test time reduction

A built-in self-test (BIST) system comprising repair logic structured to share state logic of failed memories across local registers located in a shared registry which services multiple memories, wherein each of the local registers is associated with a different memory.

Failure analysis and repair register sharing for memory BIST

A system and method control an operation of a built-in self-test (BIST) of memory devices of an integrated circuit. The method includes generating count values using a program counter, and providing a first burst of instructions to the memory devices. The method also includes controlling a chip enable signal associated with each of the memory devices according to the count values during a wait period following the providing the first burst of instructions until a second burst of instructions is provided to the memory devices. The chip enable signal of each of the memory devices defines clock cycles at which the memory device is operated and clock cycles at which the memory device is idle.

Programmable counter to control memory built in self-test

Aspects of the invention provide for reducing BIST test time for a memory of an IC chip. In one embodiment, a BIST architecture for reducing BIST test time of a memory for an integrated circuit (IC) chip, the architecture comprising: a pair of latches for receiving bursts of data from a memory; a first compression stage for receiving a burst of data and compressing the burst of data into a plurality of latches; a second compression stage for comparing the compressed bursts of data with expected data; and a logic gate for determining whether there is a fail in the burst of data.

Built-in-self-test (BIST) test time reduction

An integrated circuit chip with a built-in self-test (BIST) circuit having a BIST engine, which is electrically connected to multiple memories, which tests those multiple memories in parallel, and which incorporates an address generator. Prior to testing, the address generator generates a pair of tables. The tables include a first table, which indicates the highest decode numbers per specific bank numbers in all of the multiple memories, and a second table, which indicates the highest bank numbers per specific decode numbers in all of the multiple memories. During testing, the address generator sequentially and dynamically generates the specific test addresses to be swept and does so such that all of the specific test addresses are within a composite address space that is defined by one of the tables and by the highest maximum word line number in any of the memories. Also disclosed is an associated BIST method.

Built-in self-test (BIST) circuit and associated BIST method for embedded memories

Disclosed is a chip with a built-in self-test (BIST) circuit that incorporates a BIST engine that tests memories in parallel and that, prior to testing, dynamically sets the size of the address space to be swept. The BIST engine comprises an address generator that determines a superset of address space values associated with all the memories. This superset indicates the highest number of banks, the highest number of word lines per bank and the highest decode number for any of the memories. The address generator then generates test addresses and does so such that all test addresses are within a composite address space defined by the superset and, thereby within an address space that may, depending upon the memory configurations, be less than the predetermined maximum address space associated with such memories so as to reduce test time. Also disclosed is an associated BIST method for testing memories.

Aspects of the invention provide for decreasing the power supply demand during built-in self test (BIST) initializations. In one embodiment, a BIST architecture for reducing the power supply demand during BIST initializations, includes: a chain of slow BIST I/O interfaces; a chain of fast BIST I/O interfaces, each fast BIST I/O interface connected to a slow BIST I/O interface; and a BIST engine including a burst staggering latch for controlling a multiplexor within each of the slow BIST I/O interfaces, wherein the burst staggering latch, for a first burst signal, staggers the first burst signal to each of the slow BIST I/O interfaces, such that, during a first clock cycle, only a first slow BIST I/O interface receives the first burst signal.

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Bagalkot, India

Deepak I Hanagandi