Monolithic 3d Inc.

Sandisk Corporation

Sandisk 3d LLC

Hefei Reliance Memory Limited

Rambus Inc.

Doordash, Inc.

Sandisk Technologies Inc.

Prof Jim Inc.

Other

Georgia Tech Research Corporation

Chowbotics

Casabots Inc.

Deepak Chandra Sekar

Zvi Or-Bach

Brian Cronquist

Israel Beinglass

Nima Mokhlesi

Jan Lodewijk De Jong

Gary Bela Bronner

Zeev Wurman

Wayne Frederick Ellis

Brent Steven Haukness

Paul G Lim

Frederick Abbott Ware

Franz Kreupl

Kathirgugan Kathirasen

Sanath Bhat

Man Lung Mui

Thomas Vogelsang

Brian Richardson

Seungpil Lee

Hao Nguyen

Ze'ev Wurman

Roy E Scheuerlein

Raghuveer S Makala

Peter Rabkin

Hock C So

Levi Lalla

Klaus Florian Schuegraf

April Dawn Schricker

Mark Harold Clark

Xiying Chen

Pranav Mehta

Victoria Reidling

Isreal Beinglass

Tanmay Kumar

George Samachisa

Andrei Mihnea

Bruce Lynn Bateman

Brian Edward Richardson

Shahzad Khalid

Li Xiao

Prashanti Govindu

Andy Fu

Gandham Venkata Sai Anooj

J L De Jong

Christophe J Chevallier

Yuniarto Widjaja

Scott C Best

Er-Xuan Ping

John Eric Linstadt

Dana Lee

Dengtao Zhao

James D Meindl

Muhannad S Bakir

Chu-Chen Fu

Tapan Samaddar

Philip F S Swab

Lidia Vereen

Dat Nguyen

Elizabeth Friend

Calvin Richard King, Jr

Gang Huang

Tai Yen Chung

Mehmet Gunhan Ertosun

Maria Walley

Bing Dang

A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, where the third level is bonded to the second level; and a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors.

3D semiconductor device and structure with three levels and isolation layers

A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors each of which includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors and overlaying the second metal layer, each of first memory cells include at least one second transistor; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors and overlaying the third level, each of second memory cells include at least one fourth transistor, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one of the second transistors includes a hafnium oxide gate dielectric.

3D semiconductor device and structure with metal layers and memory cells

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the bonded includes metal to metal bonds, and where at least one of the first transistors controls power delivery to at least one of the second transistors.

3D semiconductor device and structure

A method for producing a 3D semiconductor device including: providing a first level, including a single crystal layer; forming memory control circuits in and/or on the first level which include first single crystal transistors and at least two interconnection metal layers; forming at least one second level; performing a first etch step into the second level; forming at least one third level on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor including a metal gate, where each of the second memory cells include at least one third transistor; and performing bonding of the first level to the second level, where the first level includes control of power delivery to the at least one third transistor.

Method for producing 3D semiconductor devices and structures with transistors and memory cells

A method for operating an automated food making apparatus having a motor, actuator arm, and an apparatus. The apparatus may be a paddle with flexible fins. The method rotates the paddle with a pin-shaft mechanism to dispense an ingredient placed in a canister, controls the motor automatically based on weight sensor readings, and locates a position of the actuator arm with position sensors. The same motor dispenses ingredients from a plurality of canisters. The method may have a plurality of paddle rotation and weight measurement steps until a target weight is reached. The plurality of paddle rotation steps may be unidirectional or bidirectional paddle rotation. The paddle may be rotated according to one or more paddle rotation algorithms, an error recovery algorithm, or different algorithms based on the amounts of ingredients remaining in the canister. The paddle may be rocked until the target weight is achieved.

Enhanced automated food making apparatus

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level including an oxide to oxide bond; a plurality of pixel control circuits; a third level disposed underneath the first level, where the third level includes a plurality of third transistors, where the plurality of third transistors each include a single crystal channel; and a plurality of recessed channel transistors.

Multilevel semiconductor device and structure with image sensors and wafer bonding

A 3D device includes a first level including a first single crystal layer with control circuitry which includes first single crystal transistors; a first metal layer atop first single crystal layer; a second, third, and fourth metal layer providing connections between the first transistors; at least one second level (includes a plurality of second transistors including metal gates, and a plurality of memory cells) atop the first level; a fourth metal layer above the second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid; a local power distribution grid, where the first level includes first Electrostatic Discharge (ESD) circuits, and the second level includes second ESD circuits.

3D semiconductor device and structure including power distribution grids

A 3D semiconductor memory, the memory including: a first level including first memory cells, first transistors, and a first control line, where the first memory cells each include one of the first transistors; a second level including second memory cells, second transistors, and a second control line, where the second memory cells each include one of the second transistors, where the second level overlays the first level, where the second control line and the first control line have been processed following the same lithography step and accordingly are self-aligned, where the first control line is directly connected to each source or drain of at least five of the first transistors, and where the second control line is directly connected to each source or drain of at least five of the second transistors; and an oxide layer disposed between the first control line and the second control line.

3D semiconductor memory device and structure

A multi-level semiconductor device, the device comprising: a first level comprising integrated circuits; a second level comprising at least one electromagnetic wave receiver, wherein said second level is disposed above said first level, wherein said integrated circuits comprise single crystal transistors; and an oxide layer disposed between said first level and said second level, wherein said device comprises at least one read out circuit, wherein said second level is bonded to said oxide layer, and wherein said bonded comprises oxide to oxide bonds.

Multilevel semiconductor device and structure with oxide bonding

An automated food making apparatus is described. An automated food making apparatus can include: a carousel; a dispensing apparatus shared among a plurality of canisters on the carousel, wherein at least one canister includes a paddle; and wherein the dispensing apparatus is configured to rotate the canister's paddle to dispense ingredients stored in the canister. A dispensing mechanism for an automated food making apparatus can include: an actuator arm; a motor that is adapted to rotate the actuator arm; one or more magnets embedded in the actuator arm; and one or more sensors configured to detect position of the actuator arm; wherein the actuator arm dispenses ingredients by rotating a pin located on a canister.

Automated food making apparatus

3D semiconductor device including: a first level including first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the first single-crystal transistors; a first metal layer disposed atop the first single-crystal transistors; a second metal layer disposed atop the first metal layer, a second level disposed atop the second metal layer includes second transistors and a memory array of first memory cells, a third level including second memory cells which include some third transistors, which themselves include a metal gate and is disposed above the second level; a third metal layer disposed above the third level; a fourth metal layer disposed above the third metal layer, a connective path from the third metal layer to the second metal layer with a thru second level via of a diameter less than 800 nm which also passes thru the memory array, different write voltages for different dies.

3D semiconductor memory device and structure with memory and metal layers

A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors, including metal gate) atop the third metal layer; a fourth metal layer above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid including the fifth metal layer; a local power distribution grid, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer, a layer deposited by ALD.

A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors which each includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop ('PLL') circuit or at least one Digital-Lock-Loop (“DLL”) circuit.

A method for producing a 3D semiconductor device including: providing a first level, including a single crystal layer; forming memory control circuits in and/or on the first level which include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the memory control circuits; performing a first etch step into the second level; forming at least one third level on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor including a metal gate, where each of the second memory cells include at least one third transistor; and performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.

Methods, systems, and computer readable storage media for using image processing to develop a library of facial expressions. The system can receive digital video of at least one speaker, then execute image processing on the video to identify landmarks within facial features of the speaker. The system can also identify vectors based on the landmarks, then assign each vector to an expression, resulting in a plurality of speaker expressions. The system then scores the expressions based on similarity to one another, and creates subsets based on the similarity scores.

Systems for and methods of creating a library of facial expressions

Growing community of inventors

San Jose, CA, United States of America

Deepak Chandra Sekar