Sandisk Technologies Inc.

Deepak Bharadwaj

Daniel Joseph Linnen

Kirubakaran Periyannan

Jagdish Sabde

Ashish Ghai

Avinash Rajagiri

Srikar Peesari

Shantanu Gupta

Shrikar Bhagath

Sukhminder Singh Lobana

A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

Partial memory die with inter-plane re-mapping

A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.

Partial memory die

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Santa Clara, CA, United States of America

Deepak Bharadwaj