Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Deepak Bharadwaj

Jayavel Pachamuthu

Daniel Joseph Linnen

Kirubakaran Periyannan

Jagdish Sabde

Ashish Ghai

Avinash Rajagiri

Srikar Peesari

Shantanu Gupta

Rajan Paudel

Grishma Shah

Shrikar Bhagath

Sukhminder Singh Lobana

Navkiran Kaur Sandhu

An apparatus includes control circuits configured to connect to word lines that are coupled to NAND strings. The control circuits are configured to detect a defective word line, apply single word line erase voltages to the word lines to erase memory cells of the defective word line and, with the memory cells of the defective word line in an erased state, read data from neighboring memory cells of the NAND strings.

Data recovery in nonvolatile memory with defective word line

A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory interface configured to interface with a memory having a plurality of memory blocks. Each memory block has a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one of the memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the string to string shorts in response to determining that the one of the memory blocks has the string to string shorts.

Memory controller for resolving string to string shorts

A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

Partial memory die with inter-plane re-mapping

A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.

Partial memory die

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Fremont, CA, United States of America

Deepak Bharadwaj