Freescale Semiconductor,inc.

Deepak Agrawal

Himanshu Kukreja

Rachna Lalwani

A circuit for reducing peak power during transition fault testing of an integrated circuit (IC) includes a programmable register that receives scan shift and SDI (scan data in) signals. Input and output ports of the programmable register are connected together. A multiplexer is provided that has a first input port that is maintained asserted, and a second input port connected to the output port of the programmable register. A scan shift signal, which remains asserted during a scan shift operation and de-asserted during a scan capture operation, is provided at a select input port of the multiplexer. The output of the multiplexer is provided as an input to a clock gating cell. The clock gating cell selectively provides the clock signal to the scan-chain flip-flops in the IC based on the scan shift signal and a functional enable signal, and reduces peak power during transition fault testing.

Circuit to reduce peak power during transition fault testing of integrated circuit

A system and method for scan partitioning for testing an embedded logic circuit in an integrated circuit (IC) device is provided. One or more scan partitions in the embedded logic circuit are identified. Each scan partition includes one or more scan chains of scan registers. One or more interacting registers connecting scan registers of a first scan partition and scan registers of a second scan partition are identified and combined to form an interacting scan chain. The embedded logic circuit is tested by selectively activating the scan chains of the first and second scan partitions and the interacting scan chain.

Method for partitioning scan chain

An electronic circuit includes first and second circuits that include corresponding built-in-self-test (BIST) engines to perform memory testing operations on corresponding first and second memory block and generate first and second memory repair data. A multiplexer receives the first and second memory repair data and selectively transmits the first memory repair data during a first test cycle and the second memory repair data during a second test cycle. A shadow register buffers the first memory repair data during the first test cycle and a fuse processor sequentially receives and stores the first and second memory repair data during the second test cycle.

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Ghaziabad, India

Deepak Agrawal