Stmicroelectronics Gmbh

Stmicroelectronics Pvt. Ltd.

Sicronic Remote Kg, LLC

Deepak Agarwal

Parvesh Swami

Namerita Khanna

A field programmable device is disclosed, including a plurality of logic blocks; a plurality of connections connecting the logic blocks; configuration circuitry for outputting configuration data for programming the field programmable device, the configuration circuitry providing at least one pair of outputs; and error detection circuitry for comparing the outputs to determine if there has been a configuration error.

Field programmable device

An improved Programmable Logic Device architecture that provides more efficient utilization of resources by enabling access to defined circuit elements in the domain of any Programmable Logic Block (PLB) from any other PLB in the device, by incorporating a connecting means in the routing structure for selectively connecting the input or output of the circuit element in the domain of the PLB to the common interconnect matrix connecting all the PLBs together.

Architecture for programmable logic device

A Programmable Logic Device providing reduction in power consumption for sequential logic and data storage functions, including at least one circuit arrangement configurable to function as a dual-edge-triggered flip-flop operating on a selected one or both edges of the circuit clock.

Programmable logic devices providing reduced power consumption

An electronic circuit containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation. The electronic circuit includes an improved clock distribution scheme that reduces power consumption, comprising identifying means for determining the select/deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.

Low power clock distribution scheme

A field programmable device including a plurality of logic blocks; a plurality of configurable connections; at least one switching circuit; and a plurality of lines extending at least partially through the device. In a configuration mode, the switching circuit causes configuration signals to be passed to the configurable connections via the plurality of lines and in a processing mode, the plurality of lines are used in at least one of at least one logic block and at least one connection to carry data.

The present invention is concerned with a method and apparatus for hardening logic devices. The logic device has a plurality of memory cells forming an array connected by data lines and clock lines, and the device having a further connecting line. The method comprising: receiving data on said data lines for configuring each of the memory cells. Storing data in each of the memory cells by enabling at least one of the clock lines and when the desired data has been stored, hardening the array to fix the data by selectively connecting the data and clock lines to the further line.

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Noida, India

Deepak Agarwal