Meta Platforms, Inc.

Deepa Palamadai Sundar

Harikrishna Madadi Reddy

Visalakshi Vaduganathan

Xing Cindy Chen

Techniques to optimize memory reads when computing a video quality metric are disclosed. In some embodiments, an application-specific integrated circuit for computing video quality metrics includes a set of caches configured to store neighbor pixel data for edge width searches of pixels comprising a frame of a video being analyzed for a video quality metric and a kernel configured to receive corresponding neighbor pixel data for pixels comprising a current processing block of the frame from a subset of the set of caches and simultaneously perform edge width searches for pixels comprising the current processing block to determine corresponding pixel edge width values used for computing the video quality metric.

Optimizing memory reads when computing video quality metrics

A scalable hardware accelerator configured to compute video quality metrics is disclosed. In some embodiments, an accelerator for video quality metrics comprises an application-specific integrated circuit that includes a buffer memory configured to store at least a portion of a reference frame of a video and at least a corresponding portion of a distorted frame of a transcoded version of the video and that includes a processing unit configured to receive data from the buffer memory and compute a perception-based video quality metric for the distorted frame with respect to the reference frame.

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Sunnyvale, CA, United States of America

Deepa Palamadai Sundar