Intel Corporation

Deep K Buch

Vivek Garg

Vladimir M Pentkovski

Subramaniam M Maiyuran

Varghese George

Paul M Zagacki

Edward V Gamsaragan

David Zhao

Theodros Yigzaw

Ling Cen

Vladimir Pentkovksi

Kuljit Singh Bains

Bret L Toll

Vedvyas Shanbhogue

Wei P Chen

Raanan Sade

Rajat Agarwal

Ron Gabor

Wei Wu

Shivnandan D Kaushik

Stanislav Shwartsman

Willard M Wiseman

Robert P Adler

Joseph Murray

Jing Ling

Amy L Santoni

John G Holm

Andrew M Rudoff

Hsien-Cheng Emile Hsieh

Michael K Dwyer

Sreenivas Mandava

Geetani R Edirisooriya

Kameswar Subramaniam

Kjersten E Criss

Hsien-Hsin Lee

Hsing-Min Chen

Neil Schaper

Eric Rasmussen

Gordon McFadden

Vaibhav Singh

Zhenjun Hu

A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)

Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process.

Recovery from multiple data errors

In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch identifier associated with a test patch and a second field to store a test mode indicator to request a core functionality test, and a microcode storage to store microcode to be executed by the at least one core. Responsive to the test patch identifier, the microcode may access a firmware interface table and obtain the test patch from a non-volatile storage according to an address obtained from the firmware interface table. Other embodiments are described and claimed.

Providing autonomous self-testing of a processor

An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.

Sideband parity handling

A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.

Uncore thermal management

Apparatus and methods relating to store operations are disclosed. In one embodiment, a first storage unit is to store data. A second storage unit is to store the data only after it has become detectable by a bus agent. Moreover, the second storage unit may store an index field for each data value to be stored within the second storage unit. Other embodiments are also disclosed.

Store performance in strongly ordered microprocessor architecture

In one embodiment, a controller can perform a secure clear of a poisoned indicator associated with an uncorrectable error (after recovery from the error). To this end, the controller may access a register storing an address of a memory location associated with indicator, determine whether the address corresponds to an entry in a table storing a list of such errors, and perform the clear based at least in part on the determination. Other embodiments are described and claimed.

Securely clearing an error indicator

Embodiments of the present invention relate to a system and method for providing processing capacity on demand. According to the embodiments, a processor package has a plurality of processing elements. One or more of the processing elements may be made active in response to increased demand for processing capacity based on modifiable authorization information.

Processing capacity on demand

In one aspect of the invention is a method to synchronize accesses by multiple threads to shared resources. The method entails a first thread entering a processing queue to contend for a lock on a shared resource. If a second thread exists, where the second thread is currently executing code, then the first thread may execute the critical section of code if the second thread is not currently executing the critical section; or if the second thread is currently executing the critical section of code, then the first thread may continue to contend for ownership of the shared resource until the second thread relinquishes ownership of the shared resource, or until a yield count expires.

High performance synchronization of accesses by threads to shared resources

A store operation architecture in which store operation latency and read-for-ownership (RFO) throughput are improved. Embodiments of the invention relate to a method and apparatus to improve store performance in a microprocessor by allowing out-of-order issuance of RFO operations and more efficiently using the store buffer latency periods.

Store performance in strongly-ordered microprocessor architecture

A method and machine-readable medium measure requests by threads requesting a lock to differentiate 'hot' and 'cold' locks in accordance with the level of contention for the locks. A hardware accelerator manages access to hot locks to improve performance.

Flexible acceleration of java thread synchronization on multiprocessor computers

A multiprocessor-scalable streaming data server arrangement in a multiprocessor data server having N processors, N being an integer greater than or equal to 2, includes implementing N NICs (Network Interface Cards), a first one of the N NICs being dedicated to receiving an incoming data stream. An interrupt from the first one of the N NICs is bound to a first one of the N processors and an interrupt for an nth NIC is bound to an nth processor, 0&#x3c;n&#x3c;=N. A DPC (Deferred Procedure Call) for the nth NIC is bound to the nth processor. M client connections may be tightly coupled to the nth processor via the nth NIC, M being a positive integer. P server threads may be bound to specific ones of a second through N processors. L1 (Level 1) and L2 (Level 2) caches may be defined for each of the N processors, instructions and temporal data being stored in L2 caches of the N processors and non-temporal data being stored in L1 caches of the N processors, bypassing the L2 caches.

Multiprocessor-scalable streaming data server arrangement

Growing community of inventors

Folsom, CA, United States of America

Deep K Buch