Applied Materials, Inc.

Lam Research Corporation

Applied Material, Inc.

Deenesh Padhi

Bok Hoen Kim

Hang Yu

Ganesh Balasubramanian

Xinhai Han

Derek R Witty

Juan Carlos Rocha-Alvarez

Hichem M'Saad

Sanjay G Kamath

Srinivas Gandikota

Martin Jay Seamons

Girish Anant Dixit

Sudha S Rathi

Zhijun Jiang

Karthik Janakiraman

Tza-Jing Gung

Praket Prakash Jha

Mehul B Naik

Pramit Manna

Visweswaren Sivaramakrishnan

Amit Kumar Bansal

Alexandros T Demos

Sohyun Park

Abhijit Basu Mallick

Li-Qun Xia

He Ren

Jianhua Zhou

Kang Sub Yim

Mohamad A Ayoub

Mayur G Kulkarni

Bart Jan Van Schravendijk

Christopher Dennis Bencher

Xianmin Tang

Kwangduk Douglas Lee

Thomas E Nowak

Yong Cao

Bencherki Mebarki

Mark A Fodor

Bhaskar Kumar

Michael Wenyoung Tsiang

Juan Carlos Rocha

Shailendra Srivastava

Er-Xuan Ping

David P Thompson

Sanjeev Baluja

Paul F Ma

Rui Cheng

Hu Kang

Sang-Jin Kim

Zhenjiang Cui

Mukund Srinivasan

Naomi Yoshida

Jun Qian

David Charles Smith

Dale Robert Du Bois

Ziqing Duan

Zheng John Ye

Annamalai Lakshmanan

Kevin Vincent Moraes

Mei Yin Chang

Philip Allan Kraus

Rajeev Bajaj

Mark Joseph Saly

Robin W Cheung

Robert Jan Visser

Kelvin Chan

Jian Li

Mihaela A Balseanu

Artur Kolics

Qian Fu

Thai Cheng Chua

Tom K Cho

Patrick A Van Cleemput

Amir Hamed Al-Bayati

Suketu Arun Parikh

Yue Chen

Huixiong Dai

Ren-Guan Duan

Prerna Sonthalia Goradia

George Andrew Antonelli

Yihong Chen

Ajit Balakrishna

Dmitry A Dzilno

Kaihan Abidi Ashtiani

Ramprakash Sankarakrishnan

Christopher S Ngai

Mei-Yee Shek

Diwakar N Kedlaya

Zubin Huang

Lakmal Charidu Kalutarage

Edward P Hammond

Kalyanjit Ghosh

Nagarajan Rajagopalan

Daniel Lee Diehl

Nerissa Sue Draeger

Jonghoon Baek

Sidharth Bhatia

Yuxiang May Wang

Bo Xie

Michael C Kwan

Capacitor devices containing silicon boron nitride with high boron concentration are provided. In one or more examples, a capacitor device is provided and contains a stopper layer containing silicon boron nitride and disposed on a substrate, a dielectric layer disposed on the stopper layer, vias formed within the dielectric layer and the stopper layer, metal contacts disposed on bottoms of the vias, a nitride barrier layer containing a metal nitride material and disposed on walls of the vias and disposed on the metal contacts, and an oxide layer disposed within the vias on the nitride barrier layer, wherein the oxide layer contains one or more holes or voids formed therein. The silicon boron nitride contains about 18 atomic percent (at %) to about 50 at % of boron.

PECVD of SiBN thin films with low leakage current

Exemplary deposition methods may include introducing a precursor into a processing region of a semiconductor processing chamber via a faceplate of the semiconductor processing chamber. The methods may include flowing an oxygen-containing precursor into the processing region from beneath a pedestal of the semiconductor processing chamber. The pedestal may support a substrate. The substrate may define a trench in a surface of the substrate. The methods may include forming a first plasma of the precursor in the processing region of the semiconductor processing chamber. The methods may include depositing a first oxide film within the trench. The methods may include forming a second plasma in the processing region. The methods may include etching the first oxide film, while flowing the oxygen-containing precursor. The methods may include re-forming the first plasma in the processing region. The methods may also include depositing a second oxide film over the etched oxide film.

Silicon oxide gap fill using capacitively coupled plasmas

Semiconductor processing systems and method are described that may include flowing deposition precursors into a substrate processing region of a semiconductor processing chamber, where the substrate processing region includes an electrostatic chuck. The methods may further include depositing a seasoning layer on the electrostatic chuck from the deposition precursors to form a seasoned electrostatic chuck. The seasoning layer may be characterized by a dielectric constant greater than or about 3.5. The methods may still further include applying a voltage to the seasoned electrostatic chuck of greater than or about 500 V. The seasoned electrostatic chuck may be characterized by a leakage current of less than or about 25 mA when the voltage is applied.

Systems and methods of seasoning electrostatic chucks with dielectric seasoning films

Exemplary semiconductor processing chambers may include a chamber body. The chambers may include a substrate support disposed within the chamber body. The substrate support may define a substrate support surface. The chambers may include a showerhead positioned supported atop the chamber body. The substrate support and a bottom surface of the showerhead may at least partially define a processing region within the semiconductor processing chamber. The showerhead may define a plurality of apertures through the showerhead. The bottom surface of the showerhead may define an annular groove or ridge that is positioned directly above at least a portion of the substrate support.

Shaped showerhead for edge plasma modulation

Exemplary deposition methods may include delivering a silicon-containing precursor and an inert gas to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the silicon-containing precursor and the inert gas. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a silicon-containing material on a substrate disposed within the processing region of the semiconductor processing chamber. The processing region may be maintained free of helium delivery during the deposition method.

Helium-free silicon formation

Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 Å.

Profile shaping for control gate recesses

Exemplary methods of forming semiconductor structures may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The methods may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized by an oxygen concentration greater than or about 5 at. %. The methods may also include repeating the forming a silicon oxide layer and the forming a silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride.

Modified stacks for 3D NAND

Exemplary methods of forming a silicon-and-carbon-containing material may include flowing a silicon-and-carbon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma within the processing region of the silicon-and-carbon-containing precursor. The plasma may be formed at a frequency above 15 MHz. The methods may include depositing a silicon-and-carbon-containing material on the substrate. The silicon-and-carbon-containing material as-deposited may be characterized by a dielectric constant below or about 3.0.

Systems and methods for depositing low-k dielectric films

Methods and systems are described for generating assessment maps. A method includes receiving a first vector map comprising a first set of vectors each indicating a distortion of a particular location on a substrate and generating a second vector map indicating a change in direction of a magnitude of the distortion of the particular location on the substrate. The method further includes generating a third vector map comprising vectors reflecting reduced noise in distortions across the plurality of locations on the substrate and generating a fourth vector map projecting a direction component of each vector component in the third set of vectors to a radial direction. The method further includes generating a fifth vector map by grouping the vectors of the fourth set of vectors and determining a magnitude associated with each group of vectors.

Analyzing in-plane distortion

Exemplary deposition methods may include delivering a boron-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the boron-containing precursor and the nitrogen-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the boron-containing precursor or the nitrogen-containing precursor may be greater than or about 2:1. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-nitrogen material on a substrate disposed within the processing region of the semiconductor processing chamber.

Boron nitride for mask patterning

Exemplary substrate support assemblies may include an electrostatic chuck body that defines a substrate support surface. The substrate support surface may define a plurality of protrusions that extend upward from the substrate support surface. A density of the plurality of protrusions within an outer region of the substrate support surface may be greater than in an inner region of the substrate support surface. The substrate support assemblies may include a support stem coupled with the electrostatic chuck body. The substrate support assemblies may include an electrode embedded within the electrostatic chuck body.

Low impedance current path for edge non-uniformity tuning

Exemplary substrate support assemblies may include a chuck body defining a substrate support surface. The substrate support surface may define a plurality of protrusions that extend upward from the substrate support surface. The substrate support surface may define an annular groove and/or ridge. A subset of the plurality of protrusions may be disposed within the annular groove and/or ridge. The substrate support assemblies may include a support stem coupled with the chuck body.

Mesa height modulation for thickness correction

Exemplary deposition methods may include forming a plasma of a silicon-containing precursor and at least one additional precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include depositing material on the semiconductor substrate to a target thickness. The methods may include halting delivery of the silicon-containing precursor while maintaining the plasma with the one or more precursors. The methods may include purging the processing region of the semiconductor processing chamber.

Methods for pressure ramped plasma purge

Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 &#x212b;.

Exemplary semiconductor processing systems may include a processing chamber and an electrostatic chuck disposed at least partially within the processing chamber. The electrostatic chuck may include at least one electrode and a heater. A semiconductor processing system may include a power supply to provide a signal to the electrode to provide electrostatic force to secure a substrate to the electrostatic chuck. The system may also include a filter communicatively coupled between the power supply and the electrode. The filter is configured to remove or reduce noise introduced into the chucking signal by operating the heater while the electrostatic force on the substrate is maintained. The filter may include active circuitry, passive circuitry, or both, and may include an adjustment circuit to set the gain of the filter so that an output signal level from the filter corresponds to an input signal level for the filter.

Power supply signal conditioning for an electrostatic chuck

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Sunnyvale, CA, United States of America

Deenesh Padhi