Texas Instruments Corporation

Deems R Hollingsworth

Jeffrey E Brighton

Manuel L Torreno, Jr

Timothy Alan Rost

Douglas P Verret

Michael T Welch

Ronald E McMann

Harry F Pang

Steve Thompson

Charles W Sullivan

Disclosed are apparatus and method for limiting mobile charge () ingress within a silicon-on-insulator (SOI) substrate (). A mask () is applied to the substrate to form an aperture () over a desired portion of the substrate near its outer edge. A buffer material (), selected to impede mobile charge ingress, is implanted () through the aperture into the insulator layer () of the substrate to form a buffer structure ().

Versatile system for limiting mobile charge ingress in SOI semiconductor structures

Disclosed are apparatus and method for limiting mobile charge ( ) ingress within a silicon-on-insulator (SOI) substrate ( ). A mask ( ) is applied to the substrate to form an aperture ( ) over a desired portion of the substrate near its outer edge. A buffer material ( ), selected to impede mobile charge ingress, is implanted ( ) through the aperture into the insulator layer ( ) of the substrate to form a buffer structure ( ).

A bipolar transistor formed on the face of a semiconductor substrate which includes an extrinsic base of a first conductivity type formed in a portion of an emitter-base region of said semiconductor. A conducting base contacting layer is formed over the extrinsic base which has a non-conducting spacer formed over a sidewall thereof. An intrinsic base in the emitter-base region is juxtaposed to the extrinsic base. An emitter of a second conductivity type is formed within the intrinsic base with an edge of the emitter being aligned with an outer edge of the spacer. The method includes forming an isolation trench, viewed in plan, having corners that are angled at about 45 degrees.

Polysilicon self-aligned bipolar device including trench isolation and

A method of making a bipolar transistor in an LSI or VLSI process which includes forming a buried DUF collector of a first conductivity type, growing an epitaxial layer of a first conductivity type over said DUF collector and forming isolation means around a transistor region. The transistor region includes a trench which at least partially encloses the transistor region and extends through the DUF collector. Emitter and base regions of the first and second conductivity types, respectively, are formed in the epitaxial layer. A collector contact region of the first conductivity is formed in the epitaxial layer and extends down to the buried DUF collector.

Bipolar transistor with shallow junctions and capable of high packing

A bipolar transistor formed on the face of a semiconductor substrate which includes an extrinsic base of a first conductivity type formed in a portion of an emitter-base region of said semiconductor. A conducting base contacting layer is formed over the extrinsic base which has a non-conducting spacer formed over a sidewall thereof. An intrinsic base in the emitter-base region is juxtaposed to the extrinsic base. An emitter of a second conductivity type is formed within the intrinsic base with an edge of the emitter being aligned with an outer edge of the spacer.

Bipolar transistor in isolation well with angled corners

A method of forming double polysilicon contacts to underlying diffused regions of a semiconductor body which includes forming first and second level electrically conductive silicon layers over the body which contact respective first and second diffused regions of the body. The diffused regions are formed such that said first diffused region is ringed by said second diffused region. The second silicon layer thus overlaps the first silicon layer. The top surfaces of the first and second silicon layers are silicided such that the silicide formed over the first silicon layer is aligned with the edge of the second silicon layer.

Self-aligned silicide in a polysilicon self-aligned bipolar transistor

A memory cell (10) has a bipolr decoupling element (56), (68), (82), (92) having an exterior contact (36). A refractory conductive layer (40) is formed on contact (36), and an initially nonconductive antifuse layer (48) is formed on refractory layer (40). A nonrefractory metal layer (50) is formed on the nonconductive layer (48). Blocking elements (56) (68), (82) (92) are connected to a word line (52), (78). When a specified voltage is impressed across the nonrefractory metal layer (50) and the word line (52), (78), nonrefractory metal diffuses through the initially nonconductive layer (48) to the refractory conductive layer (40) to provide a conductive path between the two.

Growing community of inventors

Missouri City, TX, United States of America

Deems R Hollingsworth