International Business Machines Corporation

Globalfoundries Inc.

Renesas Electronics Corporation

Adeia Semiconductor Bonding Technologies Inc.

Other

Freescale Semiconductor,inc.

Globalfoundries U.S. 2 LLC

Dechao Guo

Keith Kwong Hon Wong

Shu-Jen Han

Ruqiang Bao

Junli Wang

Chun-chen Yeh

Chung-Hsun Lin

Ruilong Xie

Huiming Bu

Kangguo Cheng

Heng Wu

Zuoguang Liu

Tenko Yamashita

Shogo Mochizuki

Pranita Kulkarni

Andrew Mark Greene

Wilfried Haensch

Lan Yu

Veeraraghavan S Basker

Carl John Radens

Sivananda K Kanakasabapathy

Philip Joseph Oldiges

Peng Xu

Hemanth Jagannathan

Zhen Zhang

Kuen-Ting Shiu

Rajasekhar Venigalla

Alexander Reznicek

Devendra K Sadana

Julien Frougier

Ravikumar Ramachandran

Zhengwen O Li

Unoh Kwon

Chun-Chen Yeh

Chen Zhang

Vijay Narayanan

Reinaldo Ariel Vega

Fei Liu

Xin Ru Wang

Shreesh Narasimha

Brent A Anderson

Juntao Li

Josephine B Chang

Balasubramanian Pranatharthiharan

Robert Russell Robison

Chengwen Pei

Siddarth A Krishnan

Albert Manhee Chu

Xinhui Wang

Lawrence Alfred Clevenger

Nicolas J Loubet

Oleg Gluschenkov

Christian Lavoie

Jingyun Zhang

Praneet Adusumilli

Michael Patrick Chudzik

Eduard Albert Cartier

Brian Joseph Greene

William K Henson

Edward William Kiewra

Shahab Siddiqui

Bruce Bennett Doris

Choonghyun Lee

Ghavam G Shahidi

Stephen W Bedell

Ramachandra Divakaruni

Jeehwan Kim

Judson Robert Holt

Kern Rim

Arvind Kumar

Joel Pereira De Souza

Qing Cao

Martin Michael Frank

Marwan H Khater

Kisik Choi

Yu Zhu

Jin Cai

Qintao Zhang

Richard Anthony Conti

Henry K Utomo

Viorel C Ontalus

Michael P Belyansky

Gregory Gower Freeman

Chanro Park

Mukta G Farooq

Michael A Guillorn

Andres Bryant

Leland Chang

Hsueh-Chung Chen

Sanjay C Mehta

Su Chen Fan

Ramachandran Muralidhar

John Ryan Sporre

Tze-Chiang Chen

Yun-Yu Wang

Gauri V Karve

Indira P Seshadri

Stuart A Sieg

John Christopher Arnold

Kwong Hon Wong

The embodiments herein describe a crossbar VFET where the crossbar channel (or fin) that extends between a pair of channels (fins) has reduced corner rounding, or no corner rounding. This can be achieved by developing a masking feature before etching the channels in the VFET that results in reduced, or no corner rounding in the channel structure etched using the masking feature.

Cross bar vertical FETs

A semiconductor device includes a substrate; a set of first transistors positioned on an upper surface of the substrate, each of the set of first transistors comprising a first gate and a first dielectric; an insulating layer positioned on an upper surface of the set of first transistors; and a set of second transistors positioned over the set of first transistors and with the set of first transistors on an upper surface of the insulating layer, each of the set of second transistors having a second gate and a second dielectric; wherein each of the first dielectrics is connected to a sidewall of each of a corresponding first gate; and wherein each of the second dielectrics is connected to the insulating layer.

Multi-VT solution for replacement metal gate bonded stacked FET

An interconnect layer for a device and methods for fabricating the interconnect layer are provided. The interconnect layer includes first metal structures arranged in a first array in the interconnect layer and second metal structures, arranged in a second array in the interconnect layer. The second array includes at least one metal structure positioned between two metal structures of the first metal structures. The interconnect layer also includes a spacer material formed around each of the first metal structures and the second metal structures and air gaps formed in the spacer material on each side of the first metal structures.

Electronic devices with a low dielectric constant

A semiconductor device includes a FinFET fin. The same FinFET fin is associated with a bottom FinFET and a top FinFET. The FinFET fin includes a lower channel portion, associated with the bottom FinFET, a top channel portion, associated with the top FinFET, and a channel isolator between the bottom channel portion and the top channel portion. A lower gate includes a vertical portion that is upon a sidewall of the bottom channel portion. An isolation layer may be formed upon the lower gate if it is desired for the top FinFET fin and the bottom FinFET fin to not share a gate. An upper gate is upon the top channel portion and is further upon the isolation layer, if present, or is upon the lower gate.

Upper and lower gate configurations of monolithic stacked FinFET transistors

Embodiments of the invention include vertically stacked field-effect transistors (FETs). The vertically stacked FETs include at least one first transistor and at least one second transistor separated by a dielectric isolation layer. Gate material is adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material.

Gate-cut and separation techniques for enabling independent gate control of stacked transistors

A semiconductor device is provided that includes a local passthrough interconnect structure present in a non-active device region of the device. A dielectric fill material structure is located between the local passthrough interconnect structure and a functional gate structure that is present in an active device region that is laterally adjacent to the non-active device region. The semiconductor device has reduced capacitance (and thus circuit speed is not compromised) as compared to an equivalent device in which a metal-containing sacrificial gate structure is used instead of the dielectric fill material structure.

Reduced parasitic capacitance semiconductor device containing at least one local interconnect passthrough structure

A semiconductor structure is provided that includes a first FET device stacked over a second FET device, wherein the first FET device contains a first functional gate structure containing a first work function metal and the second FET device contains a second functional gate structure containing a second work function metal. In the structure, the first work function metal is absent from an area including the second work function metal, and vice versa. Thus, no shared work functional metal is present in the semiconductor structure.

Stacked FETS with non-shared work function metals

Embodiments are disclosed for a system. The system includes multiple tracks. Further, one track includes a power rail for a first voltage. The system also includes a first via, disposed beneath, and in electrical contact with, the power rail. The system additionally includes a first contact, beneath, and in electrical contact with, the first via. The system further includes a first field effect transistor (FET), beneath, and in electrical isolation with, the first contact. Additionally, the system includes a second FET, beneath, and in electrical contact with, the first FET. Further, the system includes a second contact, beneath, and in electrical contact with, the second FET. Also, the system includes a second via, beneath, and in electrical contact with, the second contact. The system additionally includes a buried power rail (BPR), beneath, and in electrical contact with, the second via, wherein the BPR comprises a second voltage.

Vertically-stacked field effect transistor cell

A semiconductor device includes a plurality of field effect transistors (FET) formed upon semiconductor fins. Each FET includes a gate disposed transversely upon a first portion of the fins of the FET, one or more source/drain regions disposed upon the fins and in contact with the gate, and an electrically isolating layer disposed adjacent to a second portion of the fins above the gate and the source/drain regions, the electrically isolating layer having an interface with the gate. The device further includes a buried power rail (BPR) disposed between otherwise adjacent FETs. The BPR includes a metal rail extending beyond the interface into the gate, and electrically isolating sidewalls separating the metal rail from the gate and the source/drain regions. The device also includes a via-buried power rail contact disposed adjacent to the electrically isolating sidewalls, in contact with the metal rail, and in contact with one source/drain region.

Semiconductor device having a backside power rail

A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.

Backside power rails and power distribution network for density scaling

Embodiments of present invention provide a method of forming a transistor structure. The method includes receiving a first and a second gate region of a first and a second transistor, the second transistor being adjacent to the first transistor; forming a first work-function metal surrounding the first gate region; truncating the first work-function metal at a first boundary between the first transistor and the second transistor; forming one or more work-function metals surrounding the first gate region; truncating the one or more work-function metals at a second boundary between the first boundary and the second transistor; and forming another work-function metal surround the first and second gate regions. A transistor structure formed thereby is also provided.

Metal gate boundary for transistor scaling

A semiconductor structure including vertically stacked nFETs and pFETs containing suspended semiconductor channel material nanosheets (NS) and a method of forming such a structure. The structure is a three dimensional (3D) integration by vertically stacking nFETs and pFETs for area scaling. In an embodiment, vertically-stacked NS FET structures include a first nanosheet transistor located above a second nanosheet transistor; the first nanosheet transistor including a first NS channel material, wherein the first NS channel material includes a first crystalline orientation; the second nanosheet transistor including a second NS channel material, wherein the second NS channel material comprises a second crystalline orientation, the first crystalline orientation is different from the second crystalline orientation. In an embodiment, each of the respective formed vertically-stacked NS FET structures include respective suspended stack of nanosheet channels that are self-aligned with each other.

Self-aligned hybrid substrate stacked gate-all-around transistors

A semiconductor device fabrication method is provided. The semiconductor device fabrication method includes frontside semiconductor device processing on a frontside of a wafer, flipping the wafer, backside semiconductor device processing on a backside of the wafer and backside and frontside contact formation processing on the backside and frontside of the wafer, respectively.

Three-dimensional, monolithically stacked field effect transistors formed on the front and backside of a wafer

A semiconductor structure includes a first transistor device comprising a plurality of channel regions. The semiconductor structure further includes a second transistor device comprising a plurality of channel regions. The first transistor device and the second transistor device are disposed in a stacked configuration. The plurality of channel regions of the first transistor device are disposed in a staggered configuration relative to the plurality of channel regions of the second transistor device.

Staggered stacked semiconductor devices

A stacked FET structure having independently tuned gate lengths is provided to maximize the benefit of each FET within the stacked FET structure. Notably, a vertically stacked FET structure is provided in which a bottom FET has a different gate length than a top FET. In some embodiments, a dielectric spacer can be present laterally adjacent to the bottom FET and the top FET. In such an embodiment, the dielectric spacer can have a first portion that is located laterally adjacent to the bottom FET that has a different thickness than a second portion of the dielectric spacer that is located laterally adjacent the top FET.

Independent gate length tunability for stacked transistors

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Niskayuna, NY, United States of America

Dechao Guo