Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Dechang Sun

Myron Buer

David William Knebelsberger

Kevin R LeClair

Duane Jacobson

Mai T MacLennan

Brandon Bartz

Roy M Carlson

Narayana Rao Vedula

Wei Zhang

Sudeep Ashok Pomar

Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory array includes a plurality of memory cells to store data bits. Each of the plurality of memory cells includes a transistor having drain, source, and gate terminals, and a plurality of program nodes, each of the program nodes charged to a predetermined voltage and coupled to a respective one of a plurality of bit lines. For each memory cell in a subset of the plurality of memory cells, none of the plurality of program nodes is coupled to the drain terminal of the transistor to program the each memory cell in the subset of the plurality of memory cells to store at least one data bit, the at least one data bit is most occurred between the data bits.

Read-only memory (ROM) architecture with selective encoding

An encoded ROM array structure couples a first one of a first set of bitlines to a second one of a second set of bitlines through a transistor when the wordline connected to the gate terminal of that transistor is asserted. This encoded arrangement can be extended to any number of encoded bitlines, e.g., 2, 4, 8, 16, and so on. Each of the first plurality and second sets of bit lines are coupled to circuits for charging and discharging the bitlines. To read data from the first set of bit lines, the second set of bitlines is discharged, and vice versa.

Read only memory array architecture and methods of operation

Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a plurality of bit lines.

Encoded read-only memory (ROM) bitcell, array, and architecture

Read-only memory (ROM) bitcell, array, and architecture

Decoder circuits capable of decoding encoded ROM memory are provided. Embodiments provide several improvements over prior solutions which rely primarily on CMOS logic (e.g., inverters). For example, embodiments provide faster decoding by limiting the number of decoding stages to a single stage. Further, embodiments allow the use of partial swing (as opposed to full swing) on the bit lines, which results in significant power reduction. This, in turn, results in reduced amounts of capacitor discharges when reading the data.

Encoded read-only memory (ROM) decoder

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Eden Prairie, MN, United States of America

Dechang Sun