Intel Corporation

Debra T Cohen

Sung-Soo Cho

James P Kardach

Neil W Songer

John William Horigan

David I Poisner

Barnes Cooper

Leslie E Cline

Anil Nanduri

Satchit Jain

Jim S Cheng

Nader Raygani

Seyed Yahay Sotoudeh

Robert J Hunter

Chao-Hsin Chi

David A Kaysen

David Chang

Tom Willis

An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.

Entering and exiting power managed states without disrupting accelerated graphics port transactions

An element for an in home power line network is housed within the power supply of laptop computer. The element communicates with the power line and carries out network operations over that line. The device also includes logic therein which automatically detects the format of the network being communicated with so that a number of different network types can be automatically connected.

Adapter for a home power line network

The present invention provides a method and apparatus for splitting a bus target response between two devices in a computer system. In one embodiment, the computer system includes a bus having a first signal line and a second signal line, a third signal line, and two agents coupled to the bus and the third signal line. The first agent claims to be a target of a transaction on the bus without decoding the address associated with the transaction by asserting the first signal on the first signal line. The second agent responds to the transaction as the target. The second agent thereafter asserts a third signal on the third signal line to coordinate deassertion of the first signal on the first signal line by the first agent and concurrent assertion of the second signal on the second signal line by the second agent.

Method and apparatus for splitting a bus target response between two

A computer system that implements a direct memory access (DMA) request passing protocol. The computer system may comprise a Peripheral Component Interconnect (PCI) bus that includes an electrical interface as specified by a PCI Local Bus standard. The PCI bus is coupled to at least one DMA agent and a DMA controller. The DMA agent issues DMA requests to the DMA controller using the electrical interface of the PCI bus. According to one embodiment, a system I/O controller receives the DMA requests and passes them on to the DMA controller, which arbitrates the DMA requests and passes back a grant to the system I/O controller. The system I/O controller uses the electrical interface of the PCI bus to pass the grant to the DMA agent. The same DMA request passing protocol may be implemented in any bus having an electrical interface that specifies a unique request signal line for each bus agent of the bus.

Method and apparatus for handling bus master and direct memory access

A computer system performs direct memory access (DMA) transfers according to a DMA transfer protocol. The computer system may comprise a Peripheral Component Interconnect (PCI) bus that includes an electrical interface as specified by a PCI Local Bus standard. A DMA agent, system memory, and a DMA controller are coupled to the bus. The DMA controller uses the electrical interface of the PCI bus to control a DMA transfer between system memory and the DMA agent. According to one embodiment, a system I/O controller is coupled between the DMA controller and the PCI bus. The system I/O controller passes DMA control information from the DMA controller to the DMA agent using the electrical interface of the PCI bus. The electrical interface of the PCI bus includes a plurality of address lines and a grant signal line coupled to the DMA agent, wherein the system that I/O controller transmits DMA control information to the DMA agent while asserting the grant signal line.

Input output controller having interface logic coupled to DMA controller

Method and apparatus for handling bus master channel and direct memory

Growing community of inventors

Sunnyvale, CA, United States of America

Debra T Cohen