Micron Technology Incorporated

Nan Ya Technology Corporation

Other

Mircon Technology, Inc.

Debra M Bell

James S Rehmeyer

Anthony D Veches

Joshua E Alzheimer

Tyler J Gomm

Aaron Preston Boehm

Adrian J Drexler

Dale Herber Hiscock

Michael Kaminski

Libo Wang

Di Wu

Roya Baghi

Brian P Callaway

Kallol Mazumder

Seong-Hoon Lee

Zahra Hosseinimakarem

Aparna U Limaye

Diana C Majerus

Miles S Wiscombe

Shea M Morrison

Erica M Gove

Cheryl M O'Donnell

Vaughn N Johnson

Kyle Alexander

Rachael R Carlson

George B Raad

Paul A Silvestri

Brett Kenneth Dodds

Jeff A McClain

Erika Prosser

Kristen M Hopper

Greg A Blodgett

Naveh Malihi

Brian Thomas Pecha

Aaron Jannusch

Scott James Derner

Aaron M Schoenfeld

Scott Eugene Smith

Gary L Howe

Nathaniel J Meier

Markus H Geiger

Gitanjali T Ghosh

Sue-Fern Ng

Todd M Buerkle

Robert Bunnell

Stephen Michael Kaminski

Arunmozhi R Subramaniam

Deepika Thumsi Umesh

Brian T Pecha

Randall J Rooney

Scott E Smith

Eric A Becker

Michael Roth

Tyrel Z Jensen

Robert Tamlyn

Dale H Hiscock

Methods, systems, and devices for persistent health monitoring for volatile memory devices are described. A memory device may determine that an operating condition associated with an array of memory cells on the device, such as a temperature, current, voltage, or other metric of health status is outside of a range associated with a risk of device degradation. The memory device may monitor a duration over which the operating condition is outside of the range, and may determine whether the duration satisfies a threshold. In some cases, the memory device may store an indication of when (e.g., each time) the duration satisfied the threshold. The memory device may store the one or more indications in one or more non-volatile storage elements, such as fuses, which may enable the memory device to maintain a persistent indication of a cumulative duration over which the memory device is operated with operating conditions outside of the range.

Persistent health monitoring for volatile memory systems

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.

Semiconductor device with modified access and associated methods and systems

Apparatuses and methods related to memory authentication. Memory devices can be authenticated utilizing authentication codes. An authentication code can be generated based on information stored in a fuse array of the memory device. The authentication code can be stored in the memory device. The stored authentication code can be compared to a captured authentication code based on fuse array information broadcast to memory components of the memory device. The authenticity of the memory device can be determined based on the comparison and can result in placing the memory device in an unlocked state.

Memory authentication

Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, a device can be coupled to a memory device with an embedded sensor. The memory device can transmit the data generated by the embedded sensor using a sensor output coupled to the device. The memory device may generate, based at least in part on a characteristic of a memory device, a signal from a sensor embedded in the memory device and transmit the signal generated by the sensor from the memory device to another device coupled to the memory device.

Memory device sensors

Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

Memory with partial array refresh

Methods, systems, and devices for scrub rate control for a memory device are described. For example, during a scrub operation, a memory device may perform an error correction operation on data read from a memory array of the memory device. The memory device may determine a quantity of errors detected or corrected during the scrub operation and determine a condition of the memory array based on the quantity of errors. The memory device may indicate the determined condition of the memory array to a host device. In some cases, the memory device may perform scrub operations based on one or more condition of the memory array. For example, as a condition of the memory array deteriorates, the memory device may perform scrub operations at an increased rate.

Scrub rate control for a memory device

Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, another device can be coupled to a memory device with an embedded sensor. The memory device can transmit a signal representing sensor data generated by the embedded sensor using a sensor output coupled to the other device. A controller coupled to a memory device may determine one or more threshold values of a sensor or sensors embedded in a memory device. The memory device may transmit an indication responsive to one or more sensors detecting a value greater or less than a threshold and may transmit the indication to another device.

Using memory device sensors

Memory devices and systems with programmable refresh order and stagger times are disclosed herein. In one embodiment, a memory device includes a first memory bank group and a second memory bank group. The memory device is configured, in response to a refresh command, to perform a first refresh operation on the first memory bank group at a first time and a second refresh operation on the second memory bank group at a second time after the first time. The memory device is further configured to perform, in response to a read or write command, a read or write operation on the first memory bank group, the second memory bank group, or both the first and second memory bank groups after beginning the first refresh operation and before completing the second refresh operation.

Memory with programmable refresh order and stagger time

Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.

Memory with improved command/address bus utilization

Apparatuses and methods related to detecting synchronization between multiple devices. The security of a device may be compromised if the device receives commands from unauthorized sources. A state of a device can be affected by the commands the device receives. A different device can determine whether there is synchronicity between device and the different device to determine whether the security of the device may have been compromised.

Device intrusion detection via variable code comparison

Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data on which the pattern matching operation is performed may not be output from the memory during the pattern matching operation.

Apparatuses and methods for on-memory pattern matching

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may directly access a portion of memory array that is otherwise reserved for ECC functionality of a memory device. The memory array may correspond to a set of memory addresses, where each memory address of the set corresponds to a first portion of the memory array (e.g., user data plane) and to a second portion of the memory array (e.g., ECC plane). The second portion may be configured to store ECC data or second user data or metadata based on whether the ECC functionality is enabled or disabled. The memory device may determine a command directed to the memory address of the set is configured to access the first portion or the second portion based on a status of a pin associated with the command.

Semiconductor device with modified command and associated methods and systems

Growing community of inventors

Boise, ID, United States of America

Debra M Bell