International Business Machines Corporation

Debra K Korejwa

Steven H Voldman

Douglas Willard Stout

Paul Steven Zuchowski

William John Livingstone

Jeannie H Panner

Erich C Schanzenbach

Andrew D Huber

Philip S Homsinger

A integrated circuit (IC) chip with ESD robustness and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wired to I/O cells located on the chip. Unused or floating pads may be tied to a power supply or ground line, either directly or through an electrostatic discharge (ESD) protect device. A multi-supply protect device (ESDxx) coupled between pairs of supplies and ground or to return lines is also included. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection. Robust ESD protection is afforded all chip pads. The design may then be verified.

Method of automated design and checking for ESD robustness

Growing community of inventors

Charlotte, VT, United States of America

Debra K Korejwa