Texas Instruments Corporation

Debra J Dolby

John Frederic Schreck

Wayland B Holland

Catherine M Huber

David J McElroy

Phat C Truong

John Howard MacPeak

Eddie Hearl Breashears

Timmie M Coffman

Jeffrey K Kaszubinski

A semiconductor device and method of making same which includes a semiconductor substrate having a moat region with an ion implant in the moat region and a window in the substrate spaced from the moat region, electrically decoupled therefrom and having an ion implant therein in the form of a predetermined pattern. The moat region can contain one or more active and/or passive components therein. The method of fabrication comprises providing a semiconductor wafer, forming a moat region and an associated window region on the wafer, forming at least portions of electrical devices in the moat region by implanting ions therein, forming a predetermined non-electrical component pattern in the window by implanting ions in the window concurrently with the implanting of ions in the moat and completing fabrication of at least one electrical component in the moat region. Implants are verified by the above described device and selectively etching the window with an etchant selective to one of the substrate with ion implant therein and the substrate without ion implant therein to provide the pattern at a different level from the remainder of the window. The pattern is a non-electrical component pattern and the etchant is preferably selective to the portion of the window with ion implant to cause the pattern to lie below the portion of the window without ion implant.

Method of implant verification in semiconductor device using reticle

Semiconductor device with reticle specific implant verification indicator

Method of forming implant indicators for implant verification

A structure and method for improving the sense margin of nonvolatile memories is disclosed. An improvement to the sense margin of nonvolatile memories is accomplished by improving the margin both for 'ones' at low control gate voltage Vcc and for 'zeros' at high control gate voltage Vcc. Improvement in sensing at low control gate voltages Vcc is accomplished by skewing the sense amplifier response characteristics by forming the channel length of the reference memory cell to have a longer channel length than the memory cells of the array.

Skewed reference to improve ones and zeros in EPROM arrays

The memory array circuit this invention provides connection of segmented bitlines to bitline decoding circuitry while, at the same time, providing connection of combined wordlines wordline decoding circuitry. The segmentation and decoding connections permit faster speed of operation with minimal or no area penalty. The area penalty is avoided by driving common wordlines in each of the segments, effectively increasing the wordline pitch at the wordline decoder, while at the same time decreasing the number of wordline decodes required. The segmentation also permits location of the decoder circuit away from the signal and routing decode outputs.

Bitline segmentation in logic arrays

A driver circuit for applying both read and program voltages to a wordline of an integrated-circuit memory-cell logic array. The driver circuit is comprised of a series driver transistor pair, of a driver enabling means for enabling and disenabling one of the transistors of the driver transistor pair, and of a latching means. The driver transistor used during read operation may be constructed with a relatively short source-drain channel, permitting faster access speed during read operation of the circuit.

Decoder driver circuit for programming high-capacitance lines

An electrically programmable semiconductor memory device of a type having an array of programmable semiconductor floating gate transistors sets of which are coupled between associated respective source and drain lines, an array programming control transistor and a ground select transistor coupled to each of the drain and source lines. Each selected floating gate transistor in a programming mode is in series with control and ground select transistors between a high voltage Vpp and ground potential. A resistive element in series with a first conducting circuit element establishes a reference current which generates a voltage V.sub.1 at the junction of the resistive element and the circuit element. In a second current leg a second conducting circuit element, a module floating gate transistor biased into a conducting state and a module control transistor are all connected between Vpp and ground such that a voltage V.sub.2 is established at the junction of the second circuit element and the module floating gate transistor. Comparing means compares voltages V.sub.1 and V.sub.2 and adjusts the gate voltage V.sub.3 of the module programming control transistor so as to make the voltage V.sub.2 equal to voltage V.sub.1 and applies voltage V.sub.3 to the gates of the array programming control transistors. Since the transistor in the reference path is both electrically and geometrically the same as that in the second leg across which the voltage developed is compared, and is made by the same process, the current in the second leg will be substantially the same as that in the reference leg. Moreover, since the array floating gate transistors are also made by the same process as is the module floating gate transistor and the programming control and ground select transistors are also identical, by feeding the voltage V.sub.3 to array control transistors substantially the same current will flow through a selected array transistor as flows through both the reference current path and the second current leg.

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Plano, TX, United States of America

Debra J Dolby