Intel Corporation

Deborah T Marr

Eriko Nurvitadhi

Jonathan D Pearce

Elmoustapha Ould-Ahmed-Vall

Edward Thomas Grochowski

Robert Valentine

Mark Jay Charney

Amit Bleiweiss

Gilbert A Neiger

Jesus Corbal

Rajesh M Sankaran

Koichi Yamada

Thomas D Fletcher

Joseph Nuzman

Dion Rodgers

Stephen R Van Doren

Paul Caprioli

Lokpraveen B Mosur

David Lawrence Hill

Dennis Ryan Bradford

Narayan Ranganathan

Kent D Glossop

Niall D McDonnell

Richard J Greco

Kshitij Arun Doshi

Glenn J Hinton

Varghese George

Sanjeev S Jahagirdar

Avinash Sodani

Srikanth T Srinivasan

Ronak Singhal

Christopher J Hughes

Milind Baburao Girkar

James B Crossland

Ehud Cohen

Derek T Bachand

Wei W Wang

Shubhendu Sekhar Mukherjee

Christopher B Wilkerson

Sreenivas Subramoney

David A Koufaty

Nadathur Rajagopalan Satish

Wei D Wang

Wei Wang

Alaa R Alameldeen

Jong Soo Park

Sheng C Li

Mikhail Smelyanskiy

Jayesh Gaur

Asit K Mishra

Jeffrey J Cook

Ganesh Venkatesh

David B Sheffield

Nicholas P Carter

Dwight P Manley

Tracy Garrett Drysdale

Michael A O'Hanlon

Srinivas Sridharan

Dheevatsa Mudigere

John G Holm

Sebastien Hily

Dhawal Srivastava

Steven E Raasch

Anavai Ramesh

Mohammad Ashraf Bhuiyan

Sabareesh Ganapathy

Saritha Dwarakapuram

Eugene Wang

Md Faijul Amin

Niharika Maheshwari

Jesus Corbal San Adrian

Chinna B Prudvi

Adrian C Moga

Davor Capalija

Arijit Biswas

Polychronis Xekalakis

Shiv Kaushik

Abhijit Davare

Andrey Ayupov

Andrew Ling

Tomasz Czajkowski

Seth H Pugsley

Jaewoong Sim

Ariel Sabba

Anton Alexandrovich Sorokin

Desmond A Kirkpatrick

Suchit Subhaschandra

Michael A Anderson

Steven Burns

Sumeet Bandishte

Yu Wang

Srivatsan Krishnan

Mostofa Ali Patwary

Narayanan Sundaram

Jack Z Yinger

Niall D Mcdonnell

Michael A O'HANLON

An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

Machine learning accelerator mechanism

An apparatus to facilitate processing of a sparse matrix for arbitrary graph data is disclosed. The apparatus includes a graphics processing unit having a data management unit (DMU) that includes a scheduler for scheduling matrix operations, an active logic for tracking active input operands, and a skip logic for tracking unimportant input operands to be skipped by the scheduler. Processing circuitry is coupled to the DMU. The processing circuitry comprises a plurality of processing elements including logic to read operands and a multiplication unit to multiply two or more operands for the arbitrary graph data and customizable circuitry to provide custom functions.

Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanism

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Systems, methods, and apparatuses for heterogeneous computing

An apparatus to facilitate processing of a sparse matrix for arbitrary graph data is disclosed. The apparatus includes a graphics processing unit having a data management unit (DMU) that includes a scheduler for scheduling matrix operations, an active logic for tracking active input operands, and a skip logic for tracking unimportant input operands to be skipped by the scheduler. Processing circuitry is coupled to the DMU. The processing circuitry comprises a plurality of processing elements including logic to read operands and a multiplication unit to multiply two or more operands for the arbitrary graph data.

An apparatus and method for compressing floating-point values. For example, one embodiment of a processor comprises: instruction fetch circuitry to fetch instructions from a memory, the instructions including floating-point instructions; execution circuitry to execute the floating-point instructions, each floating-point instruction having one or more floating-point operands, each floating-point operand comprising an exponent value and a significand value; floating-point compression circuitry to compress a plurality of the exponent values associated with a corresponding plurality of the floating-point operands, the floating-point compression circuitry comprising: base generation circuitry to evaluate the plurality of the exponent values to generate a first base value; and delta generation circuitry to determine a difference between the plurality of exponent values and the first base value and to generate a corresponding first plurality of delta values, wherein the floating-point compression circuitry is to store the first base value and the corresponding first plurality of delta values as a plurality of compressed exponent values.

Method and system for efficient floating-point compression

Matrix multiplication systolic array feed methods and related processing element (PE) microarchitectures for efficiently implementing systolic array generic matrix multiplier (SGEMM) in integrated circuits is provided. A systolic array architecture may include a processing element array, a column feeder array, and a row feeder array. A bandwidth of external memory may be reduced by a factor of reduction based on interleaving of the matrix data via a feeding pattern of the column feeder array and the row feeder array.

Memory-size- and bandwidth-efficient method for feeding systolic array matrix multipliers

Hardware accelerator templates and design frameworks for implementing recurrent neural networks (RNNs) and variants thereof are described. A design framework module obtains a flow graph for an RNN algorithm. The flow graph identifies operations to be performed to implement the RNN algorithm and further identifies data dependencies between ones of the operations. The operations include matrix operations and vector operations. The design framework module maps the operations of the flow graph to an accelerator hardware template, yielding an accelerator instance comprising register transfer language code that describes how one or more matrix processing units and one or more vector processing units are to be arranged to perform the RNN algorithm. At least one of the one or more MPUs, as part of implementing the RNN algorithm, is to directly provide or directly receive a value from one of the one or more VPUs.

Hardware accelerator template and design framework for implementing recurrent neural networks

A processor includes a decode unit to decode an instruction that is to indicate a first source packed data operand that is to include at least four data elements, to indicate a second source packed data operand that is to include at least four data elements, and to indicate one or more destination storage locations. The execution unit, in response to the instruction, is to store at least one result mask operand in the destination storage location(s). The at least one result mask operand is to include a different mask element for each corresponding data element in one of the first and second source packed data operands in a same relative position. Each mask element is to indicate whether the corresponding data element in said one of the source packed data operands equals any of the data elements in the other of the source packed data operands.

Data element comparison processors, methods, systems, and instructions

An apparatus and method for offloading iterative, parallel work to a data parallel cluster. For example, one embodiment of a processor comprises: a host processor to execute a primary thread; a data parallel cluster coupled to the host processor over a high speed interconnect, the data parallel cluster comprising a plurality of execution lanes to perform parallel execution of one or more secondary threads related to the primary thread; and a data parallel cluster controller integral to the host processor to offload processing of the one or more secondary threads to the data parallel cluster in response to one of the cores executing a parallel processing call instruction from the primary thread.

Apparatus and method for a high throughput parallel co-processor and interconnect with low offload latency

Growing community of inventors

Portland, OR, United States of America

Deborah T Marr