International Business Machines Corporation

Advanced Micro Devices Corporation

Globalfoundries Inc.

Deborah M Massey

Nazmul Habib

Emmanuel Yashchin

Pascal A Nsame

Ernest Y Wu

Carole D Graas

John Greg Massey

Timothy Dooling Sullivan

Alvin Wayne Strong

Ping-Chuan Wang

David L Harmon

Kimball M Watson

Joseph M Lukaitis

Jason Paul Gill

Junichi Furukawa

Kanak Behari Agarwal

Ying Liu

Peter Anton Habitz

Tom C Lee

Fen Chen

Jerry D Hayes

Cathryn Jeanne Christiansen

Oliver Aubel

Prakash Periasamy

Michael Anthony Shinosky

Travis S Merrill

Stanley W Polchlopek

A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.

Optimization of integrated circuit reliability

A system for electromigration testing is disclosed. The system includes a conductive member, a cap layer of insulative material over at least a portion of a top surface of the conductive member, a cathode conductively connected to a first end of the conductive member; an anode conductively connected to a second end of the conductive member, and a current source conductively connected to the cathode and the anode. A plurality of sensory pins are disposed along a length of the conductive member between the first end and the second end of the conductive member. The sensory pins are conductively connected to a bottom surface of the conductive member. At least one measurement device is conductively connected to at least one sensory pin of the plurality of sensory pins. The at least one measurement device determines a resistance of at least one portion of the conductive member.

Electromigration testing of interconnect analogues having bottom-connected sensory pins

A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.

Method of fabricating thermally controlled refractory metal resistor

Thermally controlled refractory metal resistor

A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.

Parallel array architecture for constant current electro-migration stress testing

An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.

Enhancement of performance of a conductive wire in a multilayered substrate

Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current Ito the line; and stress testing the line while applying the constant current Isuch that the constant current Iis not altered by a resistance change due to an onset of electromigration.

IC chip stress testing

Growing community of inventors

Jericho, VT, United States of America

Deborah M Massey