Bull Hn Information Systems, Inc.

Deborah K Staplin

Jian-Kuo Shen

Richard P Kelly

Robert V Ledoux

Ming-Tzer Miu

The decoding of certain instructions cause an instruction unit of a production line data processing system to stall. Instructions still in the production line are executed, but no new instructions are sent into the production line until the instruction that caused the stall condition is executed. The execution of the instruction that caused the stall is completed by an execution unit taking over control of an address unit.

Control store addressing from multiple sources

A pipelined processing unit which includes an instruction unit stage containing logic management apparatus for processing a set of complex instructions. The logic management apparatus includes state control circuits which produce a series or sequence of control states used in tracking the different types of instructions of the complex instruction set being processed. Different ones of the states are used for different types of instructions so as to enable the different pipeline stages to operate both independently and jointly to complete the execution of different instructions of the complex instruction set.

State controlled instruction logic management apparatus included in a

A pipelined processing unit includes an instruction unit stage containing resource conflict apparatus for detecting and resolving conflicts in the use of register and indicator resources during the different phases of instruction execution. The instruction unit includes a plurality of resource registers corresponding in number to the number of instructions which can be processed concurrently by the processing unit. Decode circuits in response to each new instruction received by the instruction unit generate one or more sets of bit indication signals designating those resources required by the specific pipeline stage(s) executing the instruction for completing the execution of the instruction which are shared by those stages capable of completing the execution of instructions. Comparison circuits compare the set of bit indication signals for each new instruction that corresponds to resources needed by an earlier pipeline stage which in the preferred embodiment corresponds to a secondary execution unit, with the stored sets of bit indication signals for determining the presence of any resource conflict.

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Chelmsford, MA, United States of America

Deborah K Staplin