Unisys Corporation

Debora Y Grosse

Robert D Klein

George E Reasoner, Jr

Robert D'Aoust

David C Williams

Gerald R Smith

Stephen R Krebs

Joseph M Capo

Ravi K Nigam

Daniel R Edwards

Kevin F Jennings

Robert C Kidd

Karen A Wilds

Robert B Cording

In a system for processing and imaging documents to develop a stream of digital, video bit sets, each related to a different document is a passing array, this system including an arrangement for simultaneously compressing a number of said bit-sets for different document images and sending the results to output, this arrangement as comprising:

Document processing

A pipelined image processor generates an image of the information contained on first and second portions of a document. The pipelined image processor includes a first pipe for processing information contained on the first portion of the document, and second pipe for processing information contained on the second portion of the document. The pipes receive the output from two camera assemblies which are used for generating an electrical signal in response to information contained on the document, an image digitizer for generating digitized information from the electrical signal by the means for generating an electrical signal. In addition, both pipes also include a resequencer for generating resequenced information from the digitized information, as well as an image processor for generating processed information from the resequenced information. Finally, the first and second pipes include a transposer/compressor assembly for generating transposed and compressed information from the processed information, and a compressed data buffer for storing the transposed and compressed information.

Parallel pipelined image processor

A method and apparatus featuring the compression and decompression of the video image data on a single application specific integrated circuit (ASIC) which utilizes typical Huffman coding techniques, but which defines a run count generally as a plurality of zeros between each pair of ones and which further uses a prediction window having substantially no directional biasing errors associated therewith. Additionally, the compression/decompression apparatus of this invention utilizes a reordering technique whereby all of the 'high confidence' predictions are placed in one end of the buffer and all the 'low confidence' predictions are placed in another end of the same buffer. This reordering, together with the unbiased window configuration and associated run length count definition, allows for high efficiency lossless compression and decompression of associated image data.

Method and apparatus for lossless compression and decompression of image

An application specific integrated circuit (ASIC) allows for the transposition, compression, and decompression of acquired image video data. The transposition process associated with this ASIC provides for the reordering of received vertically scanned segments of acquired image data into horizontal rows and provides for the deleting of overscan and underscan pixel data associated with each of the vertically scanned segments of acquired data. This transposed data is then compressed. Alternatively, the application specific integrated circuit of this invention provides for the decompression of previously compressed data.

Apparatus for image data transposition and compression/decompression

A method and apparatus for the transposition of obtained video image data. This video image data originally comprises a plurality of columns, containing a plurality of pixels therein. Each of these columns uniquely corresponds to a vertical segment of the document being scanned. These vertical columns of data are then placed into an external memory and outputted therefrom, by a transposer controller, which causes the output to comprise pixel data contained in the rows of the original vertical columns input thereto.

Method and apparatus for transposing image data

A pipelined image processor is disclosed which contains a diagnostic apparatus which, under normal processing conditions, is coupled to and is in communication with resequencer, image processor, and transposer/compressor assemblies contained within the pipelined image processor. The diagnostic apparatus of this invention causes a diagnostic test pattern to be sent to the re-sequencer and image processor entities of the pipelined image processor and monitors the response thereof. This response is then used to detect faults which have occurred in these entities.

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Ann Arbor, MI, United States of America

Debora Y Grosse