International Business Machines Corporation

Debjit Sinha

Natesan Venkateswaran

Kerim Kalafala

Chandramouli Visweswariah

Vladimir P Zolotov

Jeffrey G Hemmett

Michael H Wood

Eric A Foreman

Stephen Gerard Shuma

Adil Bhanji

Gregory M Schaeffer

Vasant B Rao

Nathan C Buck

Soroush Abbaspour

Peter Anton Habitz

Robert J Allen

Eric Jason Fluhr

Hemlata Gupta

Tsung-Wei Huang

James Charles Gregerson

Jin Hu

Ravichander Ledalla

Richard W Taggart

Chaitanya Ravindra Peddawad

Douglas Keller

David James Hathaway

James Douglas Warnock

Jinjun Xiong

David J Widiger

John P Dubuque

Manjul Bhushan

Peter Feldmann

Brian M Dreibelbis

Nathaniel Douglas Hieter

Peter Claude Elmendorf

Chad Andrew Marquart

Jason David Morsey

Xiaoyue X Wang

Steven Eugene Washburn

Barry Lee Dorfman

Christine T Casey

Ayesha Akhter

Jeffrey Mark Ritzinger

Sheshashayee K Raghunathan

SheshaShayee K Raghunathan

Chaobo Li

Ravi Chander Ledalla

Vladimer Zolotov

A statistical single-input switching (SIS) timing value is obtained for a first input of a device. A side input with an arc to a common output of a circuit is selected and a statistical skew for the first input and the selected side input of the circuit is obtained. An expected-value for a statistical scale factor distribution is convolved and computed based on the statistical skew. The statistical single-input switching (SIS) timing value is scaled with a final effective statistical scale factor based on the expected-value; optionally, sensitivities of the statistical timing value to variational parameters are chain-ruled with the sensitivities of the statistical skew to variational parameters; and a statistical timing analysis of a given VLSI design is generated based on the scaled (and optionally, chain-ruled) statistical single-input switching (SIS) timing value to create the improved VLSI circuit design.

Statistical timing analysis considering multiple-input switching

The efficiency of electronic design automation is increased by building, as an electronic data structure, a timing graph characterizing a putative integrated circuit design; identifying at least one of an edge and a node in the timing graph that requires canonical timing adjustment; and electronically calculating a deterministic timing adjustment for each of a plurality of corner cases. Based on the calculated deterministic timing adjustment for each of the plurality of corner cases, the canonical timing adjustment is determined for the at least one of an edge and a node; the canonical timing adjustment is applied to the timing graph; and the timing graph is updated based on the application of the canonical timing adjustment.

Efficient projection based adjustment evaluation in static timing analysis of integrated circuits

Methods and apparatus for creating an improved VLSI design. In-context timing analysis of a nominal VLSI design is performed and at least one assigned apportionment adjustment is determined for a sub-block of the nominal VLSI design. One or more slack adjustments are derived for at least one port of the sub-block based on the at least one apportionment adjustment and the one or more slack adjustments are applied to the in-context timing analysis to simulate a post optimization version of the sub-block. The in-context timing analysis is repeated using the one or more applied slack adjustments to generate the improved VLSI design.

Apportionment aware hierarchical timing optimization

Embodiments of the present invention disclose a method, computer program product, and system for parallel access to an electronic design automation (EDA) application. The computer receives a request to access an electronic design automation (EDA) application from at least two user computing device and authenticates a user associated with each of the requests from the at least two user computing devices to access the EDA application. The computer determines a level of access to be granted to each of the user of the at least two user computing devices and creates a parallel connection to each of the at least user computing device based on the determined level of access granted to each of the users. The computer retrieves data to be transmitted to each of the at least user computing device to be displayed on each of the user computing devices and stores the data in a memory unit.

Parallel access to running electronic design automation (EDA) application

Efficiency of electronic design automation is increased by accessing a data structure characterizing a hierarchical integrated circuit design including sub-blocks each with a plurality of ports. For each given one of the ports of each of the sub-blocks, obtain a wire specification for a corresponding net connected to the given one of the ports in the design, and based on the wire specification, consult a technology-specific lookup table to determine at least one of a corresponding default driving cell and default electrical model for an external wire coupling one of the default driving cell and an actual driving cell to the given one of the ports. Optimize each of the sub-blocks out-of-context based on the at least one of default driving cells and default electrical models; verify in-context closure for the optimized sub-blocks; and, responsive to the in-context closure, update the data structure to reflect the optimized sub-blocks.

Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs

A system and method of performing variable accuracy incremental timing analysis in integrated circuit development includes generating a timing graph for interconnected components. The timing graph represents each pin as a node and each interconnection as an arc. A first node or arc is selected. First-level timing values are obtained for the first node or arc using a first timing model that provides a first level of accuracy. n timing models with corresponding n levels of accuracy are pre-selected. The first-level timing values are copied as second-level timing values and as timing values for every other one of the n levels of accuracy for the first node or arc. A second node or arc downstream from the first node or arc is selected. Second-level timing values for the second node or arc are obtained using a second timing model that provides a second level of accuracy.

Variable accuracy incremental timing analysis

The computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Multi-sided variations for creating integrated circuits

Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Creating by a computer an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

A method, system, and computer program product for performing incremental common path pessimism analysis in integrated circuit design includes performing common path pessimism removal (CPPR) analysis to provide timing credit for one or more paths that are subject to common path pessimism. The method also includes identifying one or more post-CPPR critical paths based on the CPPR analysis, setting flags for critical nodes of the one or more post-CPPR critical paths, performing a design fix to address the one or more post-CPPR critical paths, and applying a set of rules based on the design fix and the flags to identify seed points among the critical nodes of the one or more post-CPPR critical paths. Invalidating and re-performing the CPPR analysis is done only for paths associated with the seed points.

Incremental common path pessimism analysis

A system to improve performance of a semiconductor chip design includes a hierarchical analysis module that determines a hierarchical arrangement of the semiconductor chip design. The hierarchical arrangement includes a plurality of arcs located at different levels internal to the semiconductor chip design. The different levels include a macro level, a unit level and a core level. The system further includes a timing/load analysis module that determines first timing characteristics of at least one first arc in the macro level based on a first load applied to the at least one first arc. The system further determines second timing characteristics of at least one second arc in at least one of the unit level and the core level based on the first timing characteristics, with a portion of the second timing characteristics determined irrespective of the first load.

Accurate statistical timing for boundary gates of hierarchical timing models

A method, system, and computer program product perform distributed timing analysis of an integrated circuit design. Aspects include dividing the integrated circuit design into non-overlapping design partitions, each design partition including nodes and edges, each edge interconnecting a pair of the nodes. Aspects also include identifying speculative nodes among the nodes, each speculative node having at least one and less than all timing inputs available and being associated with a speculative processing task, and identifying non-speculative nodes among the nodes, each non-speculative node having all timing inputs available and being associated with a non-speculative processing task. Assigning each of the non-speculative processing tasks to a respective processor of a processing system specific to each design partition for timing analysis processing is done prior to assigning any of the speculative processing tasks.

Distributed timing analysis of a partitioned integrated circuit design

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Wappingers Falls, NY, United States of America

Debjit Sinha