Intel Corporation

Other

Debendra Mallik

Robert L Sankman

Ravindranath Vithal Mahajan

Omkar G Karhade

Sanka Ganesan

Nitin A Deshpande

Shawna M Liff

John Stephen Guzek

Srinivas V Pietambaram

Ram S Viswanath

Digvijay Ashokkumar Raorane

Amruthavalli Pallavi Alur

Chia-Pin Chiu

Robert Starkston

Bidyut K Bhattacharyya

Deepak Kulkarni

Sujit Sharan

Mathew J Manusharow

Yoshihiro Tomita

Mitul Bharat Modi

Bassam Mohammed Ziadeh

Sairam Agraharam

Ravi V Mahajan

Rahul N Manepalli

Eric Jin Li

Sriram Srinivasan

Bharat P Penmecha

Kristof Darmawikarta

Eng Huat Goh

Mihir K Roy

Je-Young Chang

Robert M Nickerson

John C Johnson

Jiun Hann Sir

Tarek A Ibrahim

Dustin P Wood

Jimin Yao

Elah Bozorg-Grayeli

Sasikanth Manipatruni

Mark T Bohr

Sasha N Oster

Kelin J Kuhn

Rajat Agarwal

Dheeraj R Subbareddy

Ravi Prakash Gutala

Ankireddy Nalamalpu

Md Altaf Hossain

Scott J Weber

Yikang Deng

Aravind Raghavendra Dasu

Sandeep B Sane

Jianyong Xie

Sri Chaitra J Chavali

William J Lambert

Joshua Heppner

Rajasekaran Swaminathan

Daewoong Suh

Chandra Mohan Jha

Hong Xie

Andrew Paul Collins

Edvin Cetegen

Andrew W Yeoh

Srikant Nekkanty

Koushik Banerjee

Sergio Antonio Chan Arguedas

Vipul V Mehta

Xiaoqian Li

Carlton E Hanna

Aastha Uppal

Johanna M Swan

Adel A Elsherbini

Ian A Young

Aleksandar Aleksov

Saikumar Jayaraman

Edward Allyn Burton

Zhichao Zhang

David Gregory Figueroa

Wilfred Gomes

Kaladhar Radhakrishnan

Brandon C Marin

James Chris Matayabas, Jr

Jeremy D Ecton

Gang Duan

Javier Soto Gonzalez

Charan K Gurumurthy

Christopher L Rumer

Joe F Walczyk

Sri Chaitra Jyotsna Chavali

Jorge Pedro Rodriguez

Doug B Ingerly

Shosaku Yamanaka

Thomas A Boyd

Manish Dubey

Yiqun Bai

Brent S Stone

Kinya Ichikawa

Xiaoying Guo

Terry Lee Sterrett

Bai Nie

Takatoshi Takikawa

Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

Ultra-thin, hyper-density semiconductor packages

Stacked die assemblies having a moisture sealant layer according to embodiments are described herein. A microelectronic package structure having a first die with a second and an adjacent third die on the first die. Each of the second and third die comprise hybrid bonding interfaces with the first die. A first layer is on a region of the first die adjacent sidewalls of the second and the third dies, and adjacent an edge portion of the first die. The first layer comprises a diffusion barrier material A second layer is over the first layer, the second layer, wherein a top surface of the second layer is substantially coplanar with the top surfaces of the second and third dies. The first layer provides a hermetic moisture sealant layer for stacked die package structures.

Moisture seal coating of hybrid bonded stacked die package assembly

An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

Nested glass packaging architecture for hybrid electrical and optical communication devices

Disclosed herein are microelectronic structures including bridges, and related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate with first and second metal layers; a cavity in the substrate, where a portion of the first and second metal layers, are exposed with the portion of the first metal layer partially overlapping the portion of the second metal layer; and a bridge component in the cavity, having a first conductive contact at a first face and a second conductive contact at a second face opposing the first face, the second face towards a bottom surface of the cavity, the portion of the first metal layer is between the second face of the bridge component and the portion of the second metal layer, and the second conductive contact is electrically coupled to the portion of the second metal layer in the cavity.

Microelectronic structures including bridges

Integrated circuit assemblies can be fabricated on a wafer scale, wherein a base template, having a plurality of openings, may cover a base substrate, such as a die wafer, wherein the base substrate has a plurality of first integrated circuit devices formed therein and wherein at least one second integrated circuit device is electrically attached to a corresponding first integrated circuit device through a respective opening in the base template. Thus, when the base substrate and base template are singulated into individual integrated circuit assemblies, the individual integrated circuit assemblies will each have a first integrated circuit that is edge aligned to a singulated portion of the base template. The singulated portion of the base template can provide an improved thermal path, mechanical strength, and/or electrical paths for the individual integrated circuit assemblies.

Edge-aligned template structure for integrated circuit packages

An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

Stripped redistrubution-layer fabrication for package-top embedded multi-die interconnect bridge

A microelectronic package structure with inorganic fill material having a first die with a second and an adjacent third die on the first die. Each of the second and third die comprise hybrid bonding interfaces with the first die. A first layer is on a region of the first die between the second and third dies. A second layer is over the first layer, the second layer comprising an inorganic dielectric material, wherein a top surface of the second layer is substantially coplanar with top surfaces of the second and third dies.

Inorganic fill material for stacked die assembly

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

Interconnect architecture with silicon interposer and EMIB

Embodiments described herein may be related to apparatuses, processes, and techniques related to micro socket arrays with fine pitch contacts to electrically couple dies, in particular photonics dies, within multichip photonics packages. In embodiments, micro socket arrays may be used in conjunction with multichip module packaging that include silicon photonic engines and optical fiber modules on the same package. In embodiments, these packages may also use a system on chip (SOC), as well as fine pitch die to die connections, for example an EMIB, that may be used to connect a PIC with an SOC. Other embodiments may be described and/or claimed.

Micro socket electrical couplings for dies

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly including a substrate having a conductive plane; and a bridge having first contacts at a first surface and second contacts at an opposing second surface, wherein the bridge is embedded in the substrate and coupled to the conductive plane in the substrate via the first contacts, wherein the bridge is coupled to a first die and a second die via the second contacts, and wherein the bridge does not include a silicon substrate.

Substrateless double-sided embedded multi-die interconnect bridge

A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

Inorganic-based embedded-die layers for modular semiconductive devices

Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

IC die and heat spreaders with solderable thermal interface structures for multi-chip assemblies including solder array thermal interconnects

Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

Heterogeneous nested interposer package for IC chips

Embodiments may relate to a microelectronic package that includes a substrate with a cavity therein. A component may be positioned within the substrate, and exposed by the cavity. A solder bump may be positioned within the cavity and coupled with the component, and a bridge die may be coupled with the solder bump. Other embodiments may be described or claimed.

Microelectronic package with substrate cavity for bridge-attach

Growing community of inventors

Chandler, AZ, United States of America

Debendra Mallik