Intel Corporation

Hewlett-Packard Development Company, L.p.

Hewlett-Packard Company

Debendra Das Sharma

Robert G Blankenship

Mahesh U Wagh

Michelle C Jen

David J Harriman

Zuoguo Wu

Ilan Pardo

Ajay V Bhatt

Venkatraman Iyer

Anil Vasudevan

Sridhar Muthrasanallur

Swadesh Choudhary

Mark B Rosenbluth

Jasmin Ajanovic

Scott Dion Rodgers

Prashant Sethi

James E Akiyama

Eran Tamari

Doron Shamia

Peter J Barry

Eliezer Weissmann

Ohad Falik

Robert J Safranek

Gerald S Pasdast

Fulvio Spagna

Daniel S Froelich

Mohan J Kumar

Jeffrey Charles Swanson

Bruce A Tennant

Balint Fleischer

Ashish Gupta

Lakshmipriya Seshan

Raj K Ramanujan

Abraham Mendelson

Narasimha Lanka

Arvind A Kumar

Yen-Cheng Liu

Simon P Johnson

Herbert H Hum

John Alan Wickeraad

Mark A Schmisseur

Kai Xiao

Adel A Elsherbini

Murugasamy K Nachimuthu

James E Jaussi

Darren S Jue

Brian S Morris

Rahul R Shah

Vedaraman Geetha

Bahaa Fahim

Aaron T Spink

Jeff Willey

Robert H Beers

Jeff C Morriss

Sitaraman V Iyer

William Harry Nale

Mohiuddin M Mazumder

Abhishek Das

Yuvraj S Dhillon

Robert A Maddox

Prahladachar Jayaprakash Bharadwaj

Avi Mendelson

Akshay G Pethe

Narasimha R Lanka

Gurushankar Rajamani

Dror Reif

Ido Y Soffair

Su Wei Lim

Kenneth C Creta

Alexander Barraclough Brown

Sean O Stalley

Sharon M Ebner

Junaid Thaliyil

Ananthan Ayyasamy

Stephen R Van Doren

Suresh S Chittor

Timothy D Wig

Ramacharan Sundararaman

Mark S Myers

Jong-Ru Guo

Joe Perry Cowan

Anil Rao

Don Soltis

David Stewart Dunning

Mahesh S Natu

Peter Onufryk

Ganapati Srinivasa

William R Bryg

Joseph Murray

Dimitrios Ziakas

Annie Foong

Abhishek Singhal

Kent Andrew Dickey

Tao Liang

Eric R Wehage

Keith A Drescher

Jayen J Desai

Richard J Glass

Ramasubramanian Rajamani

Peipei Wang

A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

Sharing memory and I/O services between nodes

Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to on-package die-to-die (D2D) interconnects. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.

On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIe) PHY

Embodiments herein relate to a clock interpolation system. The system may be configured to identify, at a change in logical state of a recovered clock signal, a logical state of a first signal when the first signal is delayed by a delay value. The system may be further configured to identify, at a change in logical state of a second signal, a logical state of the clock signal when the clock signal is delayed by the delay value. Based on the two identifications, the delay value and/or a timing of the clock signal may be adjusted. Other embodiments may be described and/or claimed.

Clock interpolation system for eye-centering

A retimer includes a first port to couple to a die over a first interconnect, where the first interconnect includes a defined set of lanes and utilizes a first communication technology, and the die is located on a first package with the retimer. The retimer further includes a second port to couple to another retimer over a second interconnect, where the second interconnect utilizes a different second communication technology, and the second retimer is located on a different, second package to facilitate a longer reach communication channel.

Retimers to extend a die-to-die interconnect

In one embodiment, a first die comprises: a first die-to-die adapter to communicate with first protocol layer circuitry via a flit-aware die-to-die interface (FDI) and first physical layer circuitry via a raw die-to-die interface (RDI), where the first die-to-die adapter is to receive message information comprising first information of a first interconnect protocol; and the first physical layer circuitry coupled to the first die-to-die adapter. The first physical layer circuitry may be configured to receive and output the first information to a second die via an interconnect, the first physical layer circuitry comprising a plurality of modules, each of the plurality of modules comprising an analog front end having transmitter circuitry and receiver circuitry. Other embodiments are described and claimed.

Standard interfaces for die to die (D2D) interconnect stacks

Embodiments herein relate to a die of a multi-die package, wherein the die is coupled with another die via a die-to-die (D2D) interconnect link. The die may transmit a data signal to the other die via a data lane of the D2D interconnect link. The die may further transmit, concurrently with the data signal, a valid signal to the other die via a valid lane of the D2D interconnect link. The valid signal may change logical state at least once during the transmission of the data signal. Other embodiments may be described and claimed.

Valid signal for latency sensitive die-to-die (D2D) interconnects

In an embodiment, an apparatus for memory access may include: a memory comprising at least one atomic memory region, and a control circuit coupled to the memory, The control circuit may be to: for each submission queue of a plurality of submission queues, identify an atomic memory location specified in a first entry of the submission queue, wherein each submission queue is to store access requests from a different requester; determine whether the atomic memory location includes existing requester information; and in response to a determination that the atomic memory location does not include existing requester information, perform an atomic operation for the atomic memory location based at least in part on the first entry of the submission queue. Other embodiments are described and claimed.

System, apparatus and methods for performing shared memory operations

In one embodiment, an apparatus includes: a die-to-die adapter to communicate with a protocol layer and physical layer circuitry, and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry, after a reset flow for the first die, is to: perform a sideband initialization of a sideband interface of the interconnect to detect that the second die has completed a reset flow for the second die; and after the sideband initialization, perform a mainband initialization of a mainband interface of the interconnect at a lowest speed, and thereafter perform a mainband training of the mainband interface at a negotiated data rate. Other embodiments are described and claimed.

Link initialization training and bring up for die-to-die interconnect

A first die has a port to couple the first die to a second die over a die-to-die interconnect. The port includes circuitry to implement a physical layer of the die-to-die interconnect, send first protocol identification data over the physical layer to identify a first protocol in a plurality of protocols, send first data over the interconnect to the second die, wherein the first data comprise data of the first protocol, send second protocol identification data over the physical layer to identify a different second protocol in the plurality of protocols, and send second data over the interconnect to the second die, wherein the second data comprise flits of the second protocol.

A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.

Shared buffered memory routing

An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

Extending multichip package link off package

In an embodiment, an apparatus includes a receiver circuit to: in response to a determination that the receiver circuit is in a high latency processing mode, transmit a hint signal to a transmitter circuit; receive a response message from the transmitter circuit; process the response message to reduce a current workload of the receiver circuit; and switch the receiver circuit from the high latency processing mode to a low latency processing mode. Other embodiments are described and claimed.

Selection of processing mode for receiver circuit

Embodiments herein relate to action that are to be taken on various lanes of a die-to-die (D2D) interconnect in the event of clock-gating. Specifically, based on identification that a clock-gating event is to occur, physical layer (PHY) logic may direct PHY electrical circuitry to set the state of various of the lanes. In some embodiments, different actions may be taken based on whether the D2D interconnect is terminated or unterminated. Other embodiments may be described and claimed.

Clock-gating in die-to-die (D2D) interconnects

A port is to couple to another die over a die-to-die (D2D) link and includes a die-to-die (D2D) adapter to determine, from a set of registers, a set of capabilities of the D2D adapter to advertise in a negotiation with a link partner D2D adapter, where the D2D adapter is on a die and the link partner D2D adapter is located on a remote link partner die. A first capabilities advertisement message is sent to the link partner D2D adapter to advertise the set of capabilities to the link partner D2D adapter. A second capabilities advertisement message is received from the link partner D2D adapter, wherein the second capabilities advertisement message identifies a set of capabilities of the link partner D2D adapter. A final configuration of a D2D link is determined to couple the die to the link partner die.

Parameter exchange for a die-to-die interconnect

In one embodiment, an apparatus comprises a first die that includes: a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to receive message information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter, the physical layer circuity comprising a plurality of second registers, where the physical layer circuitry is to receive and output the message information to a second die via an interconnect having a mainband and a sideband. During a test of the apparatus, the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers. Other embodiments are described and claimed.

Compliance and debug testing of a die-to-die interconnect

Growing community of inventors

Saratoga, CA, United States of America

Debendra Das Sharma