Cornell University

University of Notre Dame Du Lac

University of California

Govmt. of U.s.—navy

Debdeep Jena

Huili Grace Xing

Kazuki Nomoto

Zongyang Hu

Vladimir Protasenko

Wenshen Li

Grace Huili Xing

Patrick Fay

Samuel James Bader

Huili (Grace) Xing

Reet Chaudhuri

Huili Xing

Wenjun Li

Sm Islam

Shyam Bharadwaj

Umesh Kumar Mishra

Amit Lal

John David Simon

Siddharth Rajan

Benyamin Davaji

Ved Gund

Austin Hickman

Len Van Deurzen

Shubham Jadhav

Guru Bahadur Singh Khalsa

H Grace Xing

Berardi Sensale-Rodriguez

D Scott Katzer

Mingda Zhu

Jai Verma

Neeraj Nepal

John Wright

Rusen Yan

David J Meyer

Michelle M Kelly

Kevin Lee

Tian Fang

Brian P Downey

Lina Cao

Lei Liu

Henryk Turski

Alexander Austin Chaney

Bo Song

A method for achieving voltage-controlled gate-modulated light emission using monolithic integration of fin- and nanowire- n-i-n vertical FETs with bottom-tunnel junction planar InGaN LEDs is described. This method takes advantage of the improved performance of bottom-tunnel junction LEDs over their top-tunnel junction counterparts, while allowing for strong gate control on a low-cross-sectional area fin or wire without sacrificing LED active area as in lateral integration designs. Electrical modulation of 5 orders, and an order of magnitude of optical modulation are achieved in the device.

Bottom tunnel junction light-emitting field-effect transistors

A vertical gallium oxide (Ga2O3) device having a substrate, an n-type GaOdrift layer on the substrate, an, n-type semiconducting channel extending from the n-type GaOdrift layer, the channel being one of fin-shaped or nanowire shaped, an n-type source layer disposed on the channel; the source layer has a higher doping concentration than the channel, a first dielectric layer on the n-type Ga2O3 drift layer and on sidewalls of the n-type semiconducting channel, a conductive gate layer deposited on the first dielectric layer and insulated from the n-type source layer, n-type semiconducting channel as well as n-type Ga2O3 drift layer, a second dielectric layer deposited over the conductive gate layer, covering completely the conductive gate layer on channel sidewalls and an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the source contact being configured not to be in electrical contact with the conductive gate layer.

Vertical gallium oxide (GA2O3) power FETs

Solid-state devices including a layer of a superconductor material epitaxially grown on a crystalline high thermal conductivity substrate, the superconductor material being one of TiNx, ZrNx, HfNx, VNx, NbNx, TaNx, MoNx, WNx, or alloys thereof, and one or more layers of a semiconducting or insulating or metallic material epitaxially grown on the layer of superconductor material, the semiconducting or insulating material being one of a Group III N material or alloys thereof or a Group 4b N material or SiC or ScN or alloys thereof.

Expitaxial semiconductor/superconductor heterostructures

Disclosed are ferroelectric devices including devices for performing a multiplication of analog input signals and resonators. In one aspect, a ferroelectric nanoelectromechanical device includes a first structural beam, a first input electrode disposed on a first top portion of the first structural beam, and an output electrode. The apparatus further includes a first ferroelectric film disposed on a second top portion of the first input electrode, and a first resistive layer disposed on a third top portion of the first ferroelectric film, wherein a first electrode is positioned at a first end of the first resistive layer and a second electrode is positioned at a second end of the first resistive layer.

Resistive electrodes on ferroelectric devices for linear piezoelectric programming

Described herein are the design and fabrication of Group III trioxides, such as β-GaO, trench-MOS barrier Schottky (TMBS) structures with high voltage (>1 kV), low leakage capabilities, while addressing on the necessary methods to meet the requirements unique to Group III trioxides, such as β-GaO.

High voltage gallium oxide (GaO) trench MOS barrier schottky and methods of fabricating same

A High Electron Mobility Transistor (HEMT) device can include an AlN buffer layer on a substrate and an epi-GaN channel layer on the AlN buffer layer. An AlN barrier layer can be on the Epi-GaN channel layer to provide a channel region in the epi-GaN channel layer. A GaN drain region can be recessed into the epi-GaN channel layer at a first end of the channel region and a GaN source region can be recessed into the epi-GaN channel layer at a second end of the channel region opposite the first end of the channel region. A gate electrode can include a neck portion with a first width that extends a first distance above the AlN barrier layer between the GaN drain region and the GaN source region to a head portion of the gate electrode having a second width that is greater than the first width.

RF high-electron-mobility transistors including group III-N stress neutral barrier layers with high breakdown voltages

III-Nitride heterostructures with low p-type sheet resistance and III-Nitride heterostructure devices with gate recess and devices including the III-Nitride heterostructures are disclosed.

High-voltage p-channel FET based on III-nitride heterostructures

A device that includes a metal(III)-polar III-nitride substrate having a first surface opposite a second surface, a tunnel junction formed on one of the first surface or a buffer layer disposed on the first surface, a p-type III-nitride layer formed directly on the tunnel junction, and a number of material layers; a first material layer formed on the p-type III-nitride layer, each subsequent layer disposed on a preceding layer, where one layer from the number of material layers is patterned into a structure, that one layer being a III-nitride layer. Methods for forming the device are also disclosed.

Platforms enabled by buried tunnel junction for integrated photonic and electronic systems

A DUV-LED including a bottom substrate, a n-contact/injection layer formed on the bottom substrate, a p-contact region, and an emitting active region between the n-contact/injection layer and the contact region. The emitting active region includes at least one GaN quantum heterostructure. The at least one GaN quantum heterostructures is sized and shaped to determine a certain emission wavelength. Preferably, the certain emission wavelength is in a range of approximately 219-280 nm. In one embodiment, the size is controlled by precisely controlling parameters selected from the group consisting of: an epitaxial deposition time; a Ga/N ratio; a thermal annealing time; a temperature during deposition; and combinations thereof.

Light emitting diodes using ultra-thin quantum heterostructures

A polarization field assisted DUV-LED including a bottom substrate and a n-contact/injection layer formed on the bottom substrate. The n-contact/injection layer includes: a first region for accommodating strain relaxation; a second region for lateral access with a low sheet resistance and higher conductivity compared to the first region to minimize resistive losses and heat generation; and a third region of a graded vertical injection layer with low vertical resistance to minimize heat loss due to vertical resistance. The DUV-LED also includes a p-contact region, and an emitting active region between the n-contact/injection layer and the p-contact region. The injection of electrons and holes into quantum wells proceeds due to tunneling of electrons and holes under the barriers due to less than 2 nm thickness of barriers. This carrier injection lowers the Turn ON voltage of LEDs and reduces heat generation.

Polarization field assisted heterostructure design for efficient deep ultra-violet light emitting diodes

A tunnel field-effect transistor device includes a p-type GaN source layer, an ntype GaN drain layer, and an interlayer interfaced between the source-layer and the drain layer. These devices employ polarization engineering in GaN/InN heterojunctions to achieve appreciable interband tunneling current densities. In one example, the interlayer includes an Indium Nitride (InN) layer. In one example, the interlayer includes a graded Indium gallium nitride layer and an InN layer. In one example, the interlayer may include a graded Indium gallium nitride (InGaN) layer and an Indium gallium nitride (InGaN) layer. In one example, the tunnel field-effect transistor device includes an in-line configuration. In one example, the tunnel field-effect transistor device includes a side-wall configuration. In one example, the tunnel field-effect transistor device includes a nanowire cylindrical gate-all-around geometry to achieve a high degree of gate electrostatic control.

Group III-Nitride compound heterojunction tunnel field-effect transistors and methods for making the same

A tunnel field-effect transistor device includes a p-type GaN source layer, an n-type GaN drain layer, and an interlayer interfaced between the source-layer and the drain layer. In one example, the interlayer includes an Indium Nitride (InN) layer. In one example, the interlayer includes a graded Indium gallium nitride layer and an InN layer. In one example, the interlayer may include a graded Indium gallium nitride (InGaN) layer and an Indium gallium nitride (InGaN) layer. In one example, the tunnel field-effect transistor device includes an in-line configuration. In one example, the tunnel field-effect transistor device includes a side-wall configuration.

Group III-nitride compound heterojunction tunnel field-effect transistors and methods for making the same

A nitride-based field effect transistor (FET) comprises a compositionally graded and polarization induced doped p-layer underlying at least one gate contact and a compositionally graded and doped n-channel underlying a source contact. The n-channel is converted from the p-layer to the n-channel by ion implantation, a buffer underlies the doped p-layer and the n-channel, and a drain underlies the buffer.

Polarization induced doped transistor

A compositionally graded semiconductor device and a method of making same are disclosed that provides an efficient p-type doping for wide bandgap semiconductors by exploiting electronic polarization within the crystalline lattice. The compositional graded semiconductor graded device includes a graded heterojunction interface that exhibits a 3D bound polarization-induced sheet charge that spreads in accordance with &#x3c1;(z)=&#x2212;&#x2207;&#xb7;P(z), where &#x3c1;(z) is a volume charge density in a polar (z) direction, and &#x2207; is a divergence operator, wherein the graded heterojunction interface is configured to exhibit substantially equivalent conductivities along both lateral and vertical directions relative to the graded heterojunction interface.

Compositionally graded heterojunction semiconductor device and method of making same

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Ithaca, NY, United States of America

Debdeep Jena