Freescale Semiconductor,inc.

Debby Eades

Gregory S Spencer

Bich-Yen Nguyen

Mariam G Sadaka

Gauri V Karve

Ted R White

Melissa O Zavala

Joe Mogab

A semiconductor process and apparatus provides a planarized hybrid substrate () by removing a nitride mask layer () and using an oxide polish stop layer () when an epitaxial semiconductor layer () is being polished for DSO and BOS integrations. To this end, an initial SOI wafer semiconductor stack () is formed which includes one or more oxide polish stop layers () formed between the SOI semiconductor layer () and a nitride mask layer (). The oxide polish stop layer () may be formed by depositing a densified LPCVD layer of TEOS to a thickness of approximately 100-250 Angstroms.

Step height reduction between SOI and EPI for DSO and BOS integration

A semiconductor process and apparatus provide a high performance CMOS devices () with hybrid or dual substrates by etching a deposited oxide layer () using inverse slope isolation techniques to form tapered isolation regions () and expose underlying semiconductor layers () in a bulk wafer structure prior to epitaxially growing the first and second substrates () having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes () over a first substrate () that is formed by epitaxially growing (100) silicon and forming second gate electrodes () over a second substrate () that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.

Inverse slope isolation and dual surface orientation integration

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Manor, TX, United States of America

Debby Eades