Shaoxing Yuanfang Semiconductor Co., Ltd.

Siemens Aktiengesellschaft

Ningbo Aura Semiconductor Co., Limited

Debasish Behera

Raja Prabhu J

Girisha Angadi Basavaraja

Nandakishore Palla

Manikanta Sakalabhaktula

Sandeep Sasi

Sudarshan Varadarajan

Chandrashekar Bg

Srinath Sridharan

Ankit Seedher

Bhupendra Sharma

Akash Kumar Gupta

Jeevabharathi G

Purva Choudhary

Akash Gupta

Govindaraju Bv

Chandrashekar B G

Venkata Krishna Mohan Panchireddi

Ranjan Mr

Manivannan K

Chandrasekhar Bg

Pragnyasini Panigrahi

Nandini Ganig Bs

Supriya Murthy

Sapna Vandakar

An electronic block includes multiple independent Phase-Locked Loops (PLLs) and a switch matrix. Each PLL has an input path and an output path. The switch matrix is operable to concurrently connect a respective signal on the output path of each PLL to the input path of another PLL. In an embodiment, each of the respective signals on the output paths is a corresponding frequency-correction signal generated by a low-pass filter (LPF) in the corresponding PLL. In an embodiment, each PLL includes a frequency-correction signal combiner to combine the frequency-correction signals received from any of the other PLLs with its own frequency-correction signal to form a combined frequency-correction signal. The combined frequency-correction signal is provided to a controlled oscillator in the PLL to generate an output clock of the PLL based on the combined frequency-correction signal. The frequency-correction signals may be analog or digital signals.

Inter-PLL communication in a multi-PLL environment

A time-to-digital converter (TDC) includes a counter and a digital core. The counter is designed to generate a sequence of counts representing a number of transitions of interest of a first clock signal. The counter includes an asynchronous circuit and a synchronous circuit to respectively generate a first set of bits and a second set of bits of each of the sequence of numbers. The digital core is designed to process a pair of counts of the sequence.

Counter design for a time-to-digital converter (TDC)

A fractional sampling-rate converter includes a first-in first-out (FIFO) buffer, a write logic, a read logic and a fractional interpolator. The write logic is designed to write input data samples into the FIFO at a first rate. The fractional interpolator is coupled to receive the input data samples from the FIFO and is designed to generate corresponding interpolated data samples as an output of the fractional sampling-rate converter at a second rate. The read logic is designed to cause input data samples in the FIFO buffer to be transferred to the fractional interpolator. A ratio of the second rate and the first rate is a fractional number greater than one.

Fractional sampling-rate converter to generate output samples at a higher rate from input samples

A time-to-digital converter (TDC) provided according to an aspect of the present disclosure identifies existence of jitter in either one of two periodic signals received as inputs. In an embodiment, jitter is detected by examining a first sequence of counts and a second sequence of counts respectively for a first periodic signal and a second periodic signal received as input signals, with the first sequence of counts representing respective time instances on a time scale at which a first sequence of edges with a first direction of the first periodic signal occur, and the second sequence of counts representing respective time instances on the time scale at which a second sequence of edges with the first direction of the second periodic signal occur.

Time-to-digital converter (TDC) to operate with input clock signals with jitter

A time-to-digital converter (TDC) includes a count logic and a digital core. The count logic generates a first sequence of counts representing a first sequence of edges of a first periodic signal, and a second sequence of counts representing a second sequence of edges of a second periodic signal. The digital core generates a sequence of outputs representing the phase differences between the first periodic signal and the second periodic signal from the first sequence of counts and the second sequence of counts. Each output is generated from a pair of successive edges of the first direction of one of the periodic signals and an individual one of the other periodic signal occurring between the pair, and the output is set equal to the minimum of difference of the individual one with the first value of the pair and the individual one with the second value of the pair.

Time-to-digital converter (TDC) measuring phase difference between periodic inputs

A method, an apparatus, and a system for managing alarms is provided. In one aspect, the method includes detecting a fault in one of a plurality of alarm systems, wherein each of the alarm systems is configured to generate at least one alarm associated with an event in the technical installation. The method further includes invoking a proxy of the faulty alarm system upon detecting the fault condition, wherein the proxy, when invoked, is configured to perform the functions of the faulty alarm system. Additionally, the method includes processing, by the proxy, event data associated with the event in the technical installation. Furthermore, the method includes generating at least one alarm by the proxy based on the processing of the event in the technical installation and outputting an alarm condition on a device associated with a user of the technical installation.

Method, apparatus, and system for managing alarms

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Bengaluru, India

Debasish Behera