Intel Corporation

Stem-away, Inc.

Debaleena Das

Rajat Agarwal

Kai Cheng

Kuljit Singh Bains

John B Halbert

Bill Nale

Brian S Morris

Tessil Thomas

Sambaran Mitra

Ramesh Subashchandrabose

George H Huang

Mohan J Kumar

Murugasamy K Nachimuthu

John V Lovelace

Dimitrios Ziakas

Jing Ling

Sreenivas Mandava

Jonathan C Jasper

C Scott Huddleston

Reza E Daftari

Meera Ganesan

Rajat Agrawal

Systems and methods that can provide verifications and grades corresponding to items represented within ecommerce platforms such as online resume generation, online product marketplace, and online social media platforms. Evaluations of items such as skills, products, users, topics, and characteristics of users and items, contribute to verifications and grades that can be displayed in a user-friendly and understandable manner, employing graphic indicators. Contributions to the verifications and grades can be weighted according to grader profiles and item classification.

System and method for generating skill-centric online resumes with verifiable skills

A system and method associated with online resume generation which can provide skill verification of assertions contained within a resume and associated systems and methods to display the information in a user-friendly and understandable manner. Some embodiments can comprise reviews associated with the verification process to provide a confidence level indicator associated with both the review and the asserted skill in the resume.

Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.

Method and apparatus for partial cache line sparing

A method performed by a memory controller is described. The method includes, during boot up, issuing a command to a memory to cause the memory to zero out its content. The method also includes bypassing a descrambler when reading from a location in the memory that has not had its zeroed out content written over the scrambled data. The method also includes processing read data with the descrambler when reading from a location in the memory that has had its zeroed out content written over with scrambled data.

Fast boot up memory controller

Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)

Techniques and mechanisms to provide selective access to data error information by a memory controller. In an embodiment, a memory device stores a first value representing a baseline number of data errors determined prior to operation of the memory device with the memory controller. Error detection logic of the memory device determines a current count of data errors, and calculates a second value representing a difference between the count of data errors and the baseline number of data errors. The memory device provides the second value to the memory controller, which is unable to identify that the second value is a relative error count. In another embodiment, the memory controller is restricted from retrieving the baseline number of data errors.

Device, system and method to restrict access to data error information

Provided are an apparatus and method for generating common locator bits to locate a device or column error during error correction operation for a memory subsystem having memory modules, each including a plurality of memory devices. Error detection logic generates common locator bits from device bits in a plurality of memory devices in one of the memory modules. The error detection logic uses the common locator bits to locate a column across at least two of the memory devices having an error when there is a column error and to locate a memory device in the devices having an error when there is a device error. A same of the common locator bits are used to locate both one of the columns and the memory devices having errors. Error correction is performed on the located memory device or column having the error.

Apparatus and method for generating common locator bits to locate a device or column error during error correction operations

Memory subsystem error management enables dynamically changing lockstep partnerships. A memory subsystem has a lockstep partnership relationship between a first memory portion and a second memory portion to spread error correction over the pair of memory resources. The lockstep partnership can be preconfigured. In response to detecting a hard error in the lockstep partnership, the memory subsystem can cancel or reverse the lockstep partnership between the first memory portion and the second memory portion and create or set a new lockstep partnership. The detected error can be a second hard error in the lockstep partnership. The memory subsystem can create new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners. The memory subsystem can also be configured to change the granularity of the lockstep partnership when changing partnerships.

Dynamically changing lockstep configuration

Error correction in a memory subsystem includes determining whether an error is a transient error or a persistent error, and adjusting an approach to ECC (error checking and correction) based on error type. The type of error can be determined by a built in self-test. If the error is a persistent error, the memory controller can perform in erasure mode, including correcting an erasure for an identified error location prior to applying an ECC correction algorithm. Otherwise, if the error is transient, the memory controller can perform standard full ECC correction by applying the ECC correction algorithm.

Dynamic application of error correction code (ECC) based on error type

An apparatus and method are described for performing forward and reverse memory sparing operations. For example, one embodiment of a processor comprises memory sparing logic to perform a first forward memory sparing operation at a first level of granularity in response to detecting a memory failure; the memory sparing logic to perform a reverse memory sparing operation in response to a determination of an improved sparing state having a second level of granularity; and the memory sparing logic to responsively perform a second forward memory sparing operation at the second level of granularity.

Method and apparatus for reverse memory sparing

Methods, techniques, systems and apparatuses for utilizing reserved space for error correcting functionality. A cache line ('reserved line') in a plurality of cache lines to store error correcting code (ECC) data is utilized for storing ECC data corresponding to other cache lines within the plurality of cache lines when a memory device has failed.

Error correcting code scheme utilizing reserved space

In accordance with some embodiments, memory modules containing phase change memory elements may be organized so that each memory integrated circuit includes both data and error correcting code. As a result of including the error correcting code in each integrated circuit, extra accesses of the memory module to extract the error correcting code can be avoided, improving the performance of the overall memory module in some embodiments.

Memory module architecture

A novel ECC scheme is disclosed that offers an error protection level that is at least the same as (if not better than) that of the conventional ECC scheme without negatively impacting latency and design complexity. Embodiments of the present disclosure utilize an ECC scheme which leaves up to extra 2B for metadata storage by changing the error detection and correction process flow. The scheme adopts an early error detection mechanism, and tailors the need for subsequent error correction based on the results of the early detection.

Growing community of inventors

Los Gatos, CA, United States of America

Debaleena Das