Intel Corporation

Motorola Corporation

Adeia Semiconductor Bonding Technologies Inc.

Tessera LLC

Debabrata Gupta

David Gregory Figueroa

Kishore K Chakravorty

Paul H Wermer

Ilyas Mohammed

Rajesh Katkar

Laura Wills Mirkarimi

Hamid Azimi

Yukio Hashimoto

Saliya Witharana

James E Drye

Laura Mirkarimi

A microelectronic assembly includes first and second surfaces, a first thin conductive element, a first conductive projection, and a first fusible mass. The first thin conductive element includes a face that has first and second regions. The first conductive projection covers the first region of the first face. A barrier may be formed along a portion of the first region. The second face includes a second conductive projection that extends away therefrom. The first fusible metal mass connects the first conductive projection to the second conductive projection such that the first surface of the first face is oriented toward the second surface of the second substrate. The first mass extends along a portion of the first conductive projection to a location toward the first edge of the barrier. The barrier is disposed between the first thin element and the first metal mass.

Interconnect structure

A microelectronic assembly includes a first surface and a first thin conductive element exposed at the first surface and having a face comprising first and second regions. A first conductive projection having a base connected to and covering the first region of the face extends to an end remote from the base. A first dielectric material layer covers the second region of the first thin element and contacts at least the base of the first conductive projection. The assembly further includes a second substrate having a second face and a second conductive projection extending away from the second face. A first fusible metal mass connects the first projection to the second projection and extends along an edge of the first projection towards the first dielectric material layer.

To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.

Electronic assemblies comprising ceramic/organic hybrid substrate with embedded capacitors

A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.

Method of forming copper layers

Data processing system comprising ceramic/organic hybrid substrate with embedded capacitors

Low cost programmable CPU package/substrate

Electronic assembly comprising ceramic/organic hybrid substrate with embedded capacitors and methods of manufacture

A method for forming conductive interconnect bumps, such as solder bumps, on bond pads on a substrate. The method includes conductive discs and a connecting member formed between two adjacent conductive discs. The discs and connecting member are then placed over the bond pads and heat is applied so that the conductive discs and the connecting member combine to form isolated interconnect bumps. A polymer backsheet is used for support.

Process for providing interconnect bumps on a bonding pad by application

A method and apparatus for re-flow of multi-layer metal bumps. A multi layer metal bump structure is surrounded by an oxygen poor environment. The topmost layer of the metal bump structure is heated by using infrared light for a predetermined time. The infrared light has a wavelength which is selected such that the top layer is heated more than the underlying layers.

Reflow of multi-layer metal bumps

A method and means of bonding a semiconductor die (10) to a support substrate (35) using a thermosonic bonding apparatus (50). The semiconductor die (10) has bonding pads (14, 15, 17) on a first major surface (12), and the support substrate (35) has contact pads (46, 47, 44) on a principal surface (43). Hourglass shaped gold bumps (30) are formed on bonding pads (14, 15, 17). A second major surface (13) of semiconductor die (10) is secured to a thermosonic tool/end-effector (52), and the support substrate (35) is secured to a substrate chuck (48). The hourglass shaped gold bumps (30) are mated with the contact pads ( 46, 47, 44 ) on the support substrate (35). A bond is thermosonically formed between the gold bumps (30) and the contact pads (46, 47, 44).

Method of bonding a semiconductor substrate to a support substrate and

A multi-chip module (26) used to interconnect and house a plurality of integrated circuits (10). The module (26) employs an intermediate structure referred to, herein, as a bridge chip (12). The bridge chip (12) connects the integrated circuit (10) to the module substrate (19). The integrated circuit (10) is attached to the bridge chip (12) and forms a composite structure (18) which can be burned-in and tested as an individual unit. The bridge chip (12) has interconnects to bring out the inputs and outputs of the integrated circuit (10). The composite structure (18) is mounted to the module substrate (19) such that, the integrated circuit (10) has a thermal pathway to the module substrate (19), and the bridge chip (12) connects to the module substrate (19). The module substrate (19) has interconnects to connect the plurality of composite structures (18).

Growing community of inventors

Scottsdale, AZ, United States of America

Debabrata Gupta