Adeia Semiconductor Bonding Technologies Inc.

Vertical Circuits, Inc.

Other

DeAnn Eileen Melcher

Reynaldo Co

Grant Villavicencio

Weiping Pan

Scott P McGrath

Simon J S McElrea

Scott Jay Crane

Terrence Caskey

Zongrong Liu

Lawrence Douglas Andrews, Jr

Yong Du

Suzette Keefe Pangrle

Marc E Robinson

Jeffrey S Leal

Keith L Barrie

Elmer M Del Rosario

John R Bray

Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

Electrical connector between die pad and z-interconnect for stacked die assemblies

According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out.

Semiconductor die array structure

A conformal coating on a semiconductor die provides adhesion between the die and a support. No additional adhesive is necessary to affix the die on the support. The conformal coating protects the die during assembly, and serves to electrically insulate the die from electrically conductive parts that the die may contact. The conformal coating may be an organic polymer, such as a parylene, for example. Also, a method for adhering a die onto a support, which may optionally be another die, includes providing a conformal coating between the die and the support, and heating the coating between the die and the support. The conformal coating may be provided on either or both a die attach area of a surface of the die, or a die mount region of a surface of the support; and the conformal coating may be provided following placement of the die on the support.

Semiconductor die mount by conformal die coating

An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).

Wafer level surface passivation of stackable integrated circuit chips

Semiconductor die separation method

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San Jose, CA, United States of America

DeAnn Eileen Melcher