Intel Corporation

Dean Warren

Jonathan C Lueker

Kenneth B Oliver

A pipelined Universal Serial Bus (USB) parallel frame delineator and non-return to zero invert (NRZI) decoder is described. Using a three-stage pipeline and parallel data stream processing, a USB transceiver delineates received asynchronous frame boundaries within a USB peripheral NRZI data stream. Using asynchronous parallel data stream processing the USB transceiver concurrently decodes received NRZI encoded data.

Pipelined, universal serial bus parallel frame delineator and NRZI decoder

In order to recover phase information, data transmitted at a first frequency is over-sampled using a clock at a second frequency, n times per bit time to obtain n samples. The n samples are used to detect the transitions between two logic levels in said transmitted data which are stored in groups of m sets of said n edge results which are, in turn output at a clock frequency which is the second frequency divided by m, for further processing.

Data recovery method and apparatus

A concurrent asynchronous USB 2.0 data stream destuffer and separator with variable-width bit-wise memory controller is described. A parallel stream bit destuffer module identifies in parallel one or more stuffed bits in a decoded data field of a received data stream using a six-bit sliding window. The stuffed bits are bits that were inserted into the received USB data stream by a transmitter to force data transitions in the received USB data stream. A data separator module separates the one or more stuffed bits from a plurality of valid data bits in the decoded data field. A memory module generates an incremental pointer value representative of the number of valid bits and writes the plurality of valid data bits from the decoded data field into a variable sized bit-wise memory structure.

Concurrent asynchronous USB data stream destuffer with variable width bit-wise memory controller

An Ethernet switch using a hash table for address lookup. The hash function is based upon taking a slice of the coefficients of a remainder polynomial obtained after dividing the sum of an address polynomial and a shifted key polynomial by a cyclic redundancy check (CRC) polynomial. The hash table has multiple buckets for each hash table address. The switch may adaptively choose different CRC polynomials for polynomial division or different slices of the remainder polynomials to reduce bucket leakage.

Switch with adaptive address lookup hashing scheme

Incoming serial data which is received M bits at a time where M&equals;N, N&plus;1 or N&minus;1 and N is greater than 1 is synchronized to a local clock by receiving a first M bits of data, storing the first M bits, receiving M additional bits, storing the M additional bits, repetitively receiving and storing until at least a predetermined number R of bits have been stored, where R&equals;(M*X)&plus;1 where X is an integer greater than one. When this occurs, the first R bits are output and any remaining S bits in excess of R are stored and additional groups of M bits added, with the process continuing until all of a packet has been received. With this arrangement, the R bits may be output at a rate which is a fraction of the serial bit rate.

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Carlton, OR, United States of America

Dean Warren