Motorola Corporation

Codex Corporation

Adaptive Solutions, Inc.

Dean W Mueller

Ahmad H Atriss

Lanny L Parker

Stephen L Smith

Benjamin C Peterson

Daniel W Hammerstrom

Stephen G Owens

The sequencer (14) is part of a computational system (10) which includes a computational circuit component, or processor node array (16); the sequencer, or controller component (14); and a boundary interface (34) between the computational circuit component (16) and the controller component (14). The controller component (14) provides three main functions in the system: (one) it sequences computations in a computational component (16), which includes an array of processor nodes (74, 76, 78, 80, 82, 84); (two) it provides I/O processing (20) from several disparate sources between the processor node array (16) and a host processor (12); and (three) it synchronizes data flow from a substantially asynchronous portion of the system (12) with a substantially synchronous data flow in the processor node array portion of the system (16).

Neural network sequencer and interface apparatus

A phase lock loop monitors the frequency of redundant input clock signals and switches back and forth therebetween should one or the other become invalid. Thus, the PLL may continue normal operation even with a failure of one input clock signal. If both the input clock signals fail, an internal reference signal maintains the PLL at a nominal operating frequency until one of the input clock signals is restored whereby the loop can quickly re-establish phase lock. To determined validity, the input clock signals are sampled and stored by the reference signal in a predetermined manner. The input clock signal is valid if the samples of the input clock signal each have the same logic state after the sampling period; otherwise, the input clock signal is invalid if the samples of the input clock signal have at least one different logic state after the sampling period.

Circuit and method of switching between redundant clocks for a phase

A phase lock loop monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first digital signal. The first and second digital signal are applied to a lock detection circuit for generating a first digital output signal having a first logic state from a mutually exclusive combination of the first and second digital signals. The first logic state of the first digital output signal is compared with a time slot window formed by a control signal for generating a true lock detection signal when the first logic state of the first digital output signal occurs within the time slot window and a false lock detection signal when the first logic state of the first digital output signal occurs outside the time slot window.

Lock detection for a phase lock loop

Circuit and method of detecting an invalid clock signal

A combinational static CMOS logic circuit for providing a plurality of basic two-input logic functions with reduced complexity and integrated circuit area. The combinational static CMOS logic circuit provides either a NAND or an XOR output at a first output terminal and a NOR output at a second output terminal. A configuration input terminal is utilized for selecting between the NAND or the XOR output being provided at the first output terminal. In an alternate configuration, the combinational static CMOS logic circuit provides either a NOR or an XNOR output at a first output terminal and a NAND output at a second output terminal.

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Portland, OR, United States of America

Dean W Mueller