Hewlett-packard Development Company, L.p.

Intel Corporation

Dean T Lindsay

Robert D Snyder

Wayne C Ashby

Kent Andrew Dickey

John A Benavides

Kenneth D Holloway

Benjamin Dodge

David A Plettner

A method and system allows multiple compute elements to independently read and clear error register logs, discard invalid data and ensure that a user receives information stored in error log registers. Error log registers are not cleared until its information is successfully retrieved by a compute element. A counter maintains a count of errors for which detailed error information has been lost.

Method for and system producing shared usage of intercommunication fabric error logging registers in a multiprocessor environment

The present invention is a device and method to change the reflection time of a bidirectional signal so as to cause a false data value to be correctly seen as the proper data value when the bidirectional signal travels between a first semiconductor chip and a second semiconductor chip, through a transmission line between the two semiconductor chips. The reflection time is adjusted by coupling an electrical network to the transmission line to cause an early electrical reflection. In one embodiment, the network is coupled to establish an impedance discontinuity between the board trace and the package trace.

Device and method to cause a false data value to be correctly seen as the proper data value

According to one embodiment a system is disclosed. The system includes a first integrated circuit (IC) a first interface coupled to the first IC and a second IC coupled to the interface. The first IC transmits the state of each of a plurality of signals not associated with the interface to the second IC in-band via the interface each time that a change in the state of one of the plurality of signals is detected.

Mechanism to repeat signals across an unrelated link

A method and apparatus for providing a synchronization mechanism to control accesses to a non-cached shared resource by devices connected by a high speed interconnect is herein described. A semaphore is used to control access to a shared resource which is implemented by a pair of semaphore registers. A previous semaphore register is used to store the previous owner of the semaphore and a current semaphore register is used to either store the current owner of the semaphore or indicate that the semaphore is available. The current semaphore register is updated when the semaphore is available and is being taken or when the semaphore is being freed. The previous semaphore register is updated when the semaphore is freed.

Apparatus and method for synchronizing multiple accesses to common resources

Disclosed is a method and device for creating probe masks. In one embodiment, the mask aids in locating and accessing a pad on a PCB to allow for the measurement a signal at the pad using a probe. The mask is a perforated insulating sheet having holes corresponding to the spacing of at least some of the conductive pads on the PCB, and at least some of the holes are marked to aid in signal measurement. A processing system is used to assist in creating the markings.

System and method for creating probe masks

A method and apparatus are disclosed for improving the repeatability of a system during testing by ensuring that the machine state remains the same on every test. In particular, the system ensures that the polling block of a cross-bar chip is reset to the same point in the polling sequence and to the same port upon the start of every test. The system uses a global framing clock (&ldquo;GFC&rdquo;) as a common timing reference. Before executing test code, the system becomes idle and waits for a rising edge of the GFC. The system then sends a message across existing links from the monarch processor performing the test to a cache controller chip. The cache controller chip waits for a GFC edge and then sends a reset message to the cross-bar chip to reset the CSR polling block. The cross-bar chip receives the signal and resets the CSR polling block.

Method and apparatus for causing computer system interconnection to be in the same state each time test code is executed

A system and method of mapping a network topology in a network including a plurality of nodes which communicate over dedicated links which connect pairs of the nodes, where the method consists of the steps of exchanging respective network identification information between adjacent pairs of nodes, establishing communications with another of the nodes using the network identification information, obtaining network identification information of the other node from that node, using the network identification information to establish communications with other nodes, obtaining additional network identification information from those other nodes, repeating these steps until network identification information is obtained from all of the nodes of the network and using this information determine the network topology.

Protocol for identifying components in a point-to-point computer system

A system and method for testing at least one interface of a digital integrated circuit while at least one other interface of the digital integrated circuit operates in a normal mode is disclosed. Each interface includes at least one boundary scan cell such that each boundary scan cell is electrically coupled to a pin of the digital integrated circuit. The method includes selectively categorizing at least one interface into a first category. At least one other interface is selectively categorized into a second category. A first mode signal is provided to the interfaces categorized into the test mode category such that the interfaces categorized into the test mode category operate in a test mode. A second mode signal is provided to the interfaces categorized into the normal operation mode category such that the interfaces categorized into the normal operation mode category operate in a normal operation mode.

Growing community of inventors

Milpitas, CA, United States of America

Dean T Lindsay