Intel Corporation

Nytell Software LLC

Other

Dean Stuart Susnow

Richard D Reohr, Jr

Brian M Leitner

Dominic J Gasbarro

Tom E Burton

Brian M Collins

Ni Jie

Timothy Barilovits

A field programmable object array integrated circuit has video data compression capability. The integrated circuit comprises an array of programmable objects and a video compression co-processor communicatively coupled to the array of objects. The video compression co-processor comprises a set of search engines and a subpixel engine. The subpixel engine can interpolate subpixels from integer pixels and shift the integer pixels by a predetermined number of subpixels. The search engines can perform a plurality of sum of absolute differences (SAD) computations between search window pixels and macroblock pixels to locate the best SAD value using either integer pixels and/or the interpolated subpixels.

Field programmable object array having image processing circuitry

Field programmable object array and video compression processor for video data compression

Commands are passed between first and second asynchronous clock domains. Unique coded command signals are inserted into a data stream transmitted from the first asynchronous clock domain to the second asynchronous clock domain. They are passed without change from the first asynchronous clock domain to the second asynchronous clock domain through an elastic buffer. The unique coded command signals are then decoded in receiver circuitry in the second asynchronous clock domain. Process circuitry in the second asynchronous clock domain is controlled according to the decoded command signals.

Synchronization of network communication link

A technique for de-skewing a group of serial data signals respectively outputted from a group of data lanes includes simultaneously feeding a test signal to inputs of the group of data lanes and monitoring respective outputs thereof. A predetermined data element of the test signal outputted from each of the group of data lanes is respectively detected and respective elapsed times from the detection of the predetermined data element outputted from each of the group of data lanes to the detection that the predetermined data element has been outputted from all of the group of data lanes are measured. The group of serial data signals are then de-skewed by respectively delaying them in accordance with their respective measured elapsed times. The test signal may include the predetermined data element, a lane identifier, and a predetermined number of additional data symbols, the predetermined data element being a predetermined data character. The elapsed times may be measured by a group of lane tolerance counters, each counter initiating counting upon the detection of the predetermined data element in its data lane and each counter stopping counting upon the detection that the predetermined data element has been outputted from all of the group of data lanes. The group of serial data signals may be respectively delayed by a group of registers and the amount of delay of each data signal may be selected by a respective multiplexer connected to the group of registers, each multiplexer being controlled by its respective counter.

Multi-lane receiver de-skewing

A device to create, receive, and transmit packets of data in a packet switching network. This device employs a direct memory access packet controller which would interface between memory contained within a computer system and a packet switched network. This direct memory access packet controller would utilize one or more micro-engines that would dynamically allocate buffer space to process received packets of data. This direct memory access packet controller would further utilize a transmit cell FIFO circuit to allocate buffer space to packets being transmitted. In addition, a sequencer would act to control the workflow of packets being received and transmitted.

Device to receive, buffer, and transmit packets of data in a packet switching network

Some embodiments of the present invention include data network comprising a host system having a host-fabric adapter; at least one remote system; a switch fabric which interconnects said host system via said host-fabric adapter to said remote system along different physical links for data communications; and at least one communication port provided in the host-fabric adapter of the host system including a set of transmit and receive buffers capable of sending and receiving data packets concurrently via respective transmitter and receiver at an end of a physical link, via the switched fabric, and a flow control mechanism utilized to prevent loss of data due to receive buffer overflow at the end of the physical link. Other embodiments are described and claims.

Link level packet flow control mechanism

A technique for de-skewing a group of serial data signals respectively outputted from a group of data lanes includes simultaneously feeding a test signal to inputs of the group of data lanes and monitoring respective outputs thereof. A predetermined data element of the test signal outputted from each of the group of data lanes is respectively detected and respective elapsed times from the detection of the predetermined data element outputted from each of the group of data lanes to the detection that the predetermined data element has been outputted from all of the group of data lanes are measured. The group of serial data signals are then de-skewed by respectively delaying them in accordance with their respective measured elapsed times. The test signal may include the predetermined data element, a lane identifier, and a predetermined number of additional data symbols, the predetermined data element being a predetermined data character. The elapsed times may be measured by a group of lane tolerance counters, each counter initiating counting upon the detection of the predetermined data element in its data lane and each counter stopping counting upon the detection that the predetermined data element has been outputted from all of the group of data lanes. The group of serial data signals may be respectively delayed by a group of registers and the amount of delay of each data signal may be selected by a respective multiplexer connected to the group of registers, each multiplexer being controlled by its' respective counter.

An Elastic Buffer is provided to process data in a computer network and a write controller is provided to control memory storage operation of such an Elastic Buffer. The write controller may comprise a comparator mechanism which detects if link data from a source contains an IDLE signal; a Jabber counter mechanism which counts each cycle of a link clock in which an IDLE signal is not detected, and resets the count each time the IDLE signal is detected, and which asserts a DISABLE signal for a single link clock cycle if a count value reaches a programmed time-out value; and a logic gate which logically combines outputs from the comparator mechanism and the Jabber counter mechanism to generate a Write control signal for prohibiting a corresponding link data sequence from being stored in memory storage of the Elastic Buffer so as to prevent data overflow in the memory storage.

Jabber counter mechanism for elastic buffer operation

A communication link is synchronized by a network interface having a transmitter in a core clock domain different from the link clock domain of the communication link. A link synchronization state machine controls the link synchronization process. The functionality of the link synchronization state machine is partitioned so that some of the functions of the link synchronization process are performed by the transmitter in the core clock domain.

Communication link synchronization method

A network interface controller connects a processing system to receive data from a network fabric through a serial link. The data on the link is clocked in a link clock domain that is different than the core clock domain of the network interface controller. A physical interface operates in the link clock domain. It has a pipeline architecture partitioned into an input register block, a decoder block and a link synchronization manager. The input register block receives the link clock and the data on the link, and transfers the data into the link clock domain. The decoder block has dual cascaded 8B/10B decoders receiving and decoding the data transferred by the input register block. The link synchronization manager manages the synchronization of the serial link according to the decoded data. An elastic buffer is connected to the output of the link synchronization manager. It is configured to output the decoded data in the core clock domain.

Network channel receiver architecture

Method and apparatus for link physical error tracking that includes a one or more shift registers, one or more counters, and a comparator. The shift register receives one or more status bits for an input data stream denoting whether bytes of the input data stream have a link physical error. The counter increments an error count when receiving at least one status bit that denotes a link physical error, and decrements the error count when receiving at least one status bit from an output of the shift register that denotes a link physical error. The comparator compares the error count with a maximum value. A retrain signal is generated if the error count becomes larger than or equal to the maximum value. The retrain signal may be used to signal that a connection between two nodes needs to be retrained to get the two nodes back into synchronization. Link physical errors that occur aligned and misaligned with a rising edge of a symbol clock are trackable.

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Portland, OR, United States of America

Dean Stuart Susnow