Sun Microsystems, Inc.

Netlogic Microsystems, Inc

Xilinx, Inc.

Dean Liu

Pradeep R Trivedi

Claude R Gauthier

Brian W Amick

Tyler J Thorp

Sudhakar Bobba

Stefanos Sidiropoulos

Marc Loinaz

Nikhil Acharya

Gin S Yee

R Shekhar Narayanaswami

Donald C Stark

Spencer Montgomery Gold

Aninda K Roy

Kamran Zarrineh

Prasun K Raha

Pak Shing Chau

Warren E Cory

Clemenz Lenard Portmann

Lynn Ooi

Kian Chong

R Sekhar Narayanaswami

A circuit for clocking includes an input data path, a receiver, a set of flip-flops, at least one interpolator and a controller. The receiver is coupled to the input data path for receiving input data. The flip-flops, coupled to the receiver, sample the input data. A first interpolator, coupled to one or more of the flip-flops, receives the sampled input data. The controller, coupled to the first interpolator, controls the first interpolator by providing phase information regarding the input data to the first interpolator. The circuit reduces any jitter transferred from the input path to an output path.

Repeate architecture with single clock multiplier unit

A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Methods and apparatus for frequency synthesis with feedback interpolation

A method and apparatus for a multiple lane transmission system that provides both a low latency mode of operation, while at the same time, provides reduced lane-lane skew. The overall transmission system operates as a mesochronous system, whereby each clock domain of the transmission system is synchronized to the leaf nodes of a global clock tree. A phase aligner is then used to align the phase of both the bit and byte clocks of each transmission lane to the clock signal generated at the leaf nodes of the global clock tree.

Method and apparatus for a mesochronous transmission system

Data and clock synchronization within a gigabit receiver is maintained throughout the data byte processing logic of the receiver by utilizing the same byte clock signal. The deserialization clock signal that is used to deserialize the received serial data stream is phase coherent with the distributed byte clock signal used within the physical coding sublayer (PCS), thus establishing reliable data transfer across the physical media attachment (PMA) and PCS layers of the gigabit receiver while maintaining a known, fixed latency. The phase relationship between a derived bit clock signal and the byte clock signal is shifted in a manner that achieves coarse data alignment within each data byte without affecting the latency. Conversely, the coarse data alignment is combined with a data alignment toggling procedure to reduce data alignment granularity with minimized latency changes.

Method and apparatus for receive channel data alignment with minimized latency variation

A method and apparatus for a receive equalizer of a gigabit transceiver that is reconfigurable to support multiple communication standards. Communication standards having variable common mode and coupling requirements are accommodated through the use of reconfigurable integrated circuits (ICs), such as field programmable gate arrays (FPGAs), that provide a plurality of reconfigurable transceivers that are programmable through configuration, or partial reconfiguration, events. The reconfigurable transceivers apply internally generated common mode voltage signals to the differential input in support of the various communication standards.

Method and apparatus for a programmably terminated receiver

Methods and apparatus for minimizing jitter in a clock synthesis circuit that uses feedback interpolation

Methods and apparatus for generating multiple clocks using feedback interpolation

A calibration and adjustment system for post-fabrication control of a delay locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the delay locked loop.

Method and apparatus to store delay locked loop biasing parameters

A mixed signal delay locked loop characterization technique for automatically characterizing a mixed signal delay locked loop is provided. The technique tests the mixed signal delay locked loop using a top-down approach in order to ensure the robustness of the mixed signal delay locked loop. Top-level testing involves testing the performance of the mixed signal delay locked loop in different process corners, and the results obtained from the top-level testing are then used to test sub-components of the mixed signal delay locked loop.

Mixed signal delay locked loop characterization engine

An adjustment and calibration system for post-fabrication treatment of a phase locked loop input receiver is provided. The adjustment and calibration system includes at least one adjustment circuit, to which the phase locked loop input receiver is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.

Adjustment and calibration system for post-fabrication treatment of phase locked loop input receiver

A technique for adjusting a communication system involves a link, where the link includes a data line arranged to transmit a data signal and a clock line adapted to transmit a clock signal. The technique uses one or more counters to test the transmission across the link. Dependent on one or more of these counters, a test circuit, connected to the link, compares a known test pattern signal to a latched test pattern signal transmitted on the data line. The test circuit includes an adjustment circuit arranged to generate an adjustable clock signal from the clock signal, where the adjustable clock signal determines when to latch the transmitted test pattern signal The test circuit adjusts a timing of the adjustable clock signal relative to the data signal of the link.

Updating high speed parallel I/O interfaces based on counters

A device that uses an input clock signal to generate an output clock signal with a desired frequency is provided. The device uses a voltage controlled delay element that outputs a reset signal to a flip-flop dependent on a bias signal and the input clock signal. When triggered, the flip-flop outputs a transition on the output clock signal, which, in turn, serves as an input to a duty cycle corrector that generates the bias signal dependent on the configuration of the duty cycle corrector. The duty cycle corrector may be configured to generate the bias signal so as to be able to operatively control the duty cycle of the output clock signal.

Duty cycle corrector

A method for estimating jitter in a phase locked loop is provided. The estimation is determined from a simulation that uses a representative power supply waveform having noise as an input. Further, a computer system for estimating jitter in a phase locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to estimate jitter in a phase locked loop is provided.

Jitter estimation for a phase locked loop

A delay locked loop implementing design-for-test features to test for, among other, stuck-at-faults is provided. The delay locked loop uses multiplexers as design-for-test devices for controllability purposes and flip-flops as design-for-test devices for observability purposes. Such implementation of design-for-test features within a delay locked loop allows for pre-packaging delay locked loop verification and testing.

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Sunnyvale, CA, United States of America

Dean Liu