Micron Technology Incorporated

Avalanche Technology, Inc.

Intel Corporation

Dean K Nobunaga

Frankie F Roohparvar

June Lee

Chih Liang Chen

Ebrahim Abedifard

Uday Chandrasekhar

Hanqing Li

Eric N Lee

Terry M Grunzke

Xiaojiang Guo

Ali Feiz Zarrin Ghalam

Luyen Tien Vu

William Kammerer

Ali Ghalam

Jason Guo

The present invention is directed to a nonvolatile memory device including a plurality of memory cells arranged in rows and columns, a plurality of word lines with each connected to a respective row of the memory cells along a row direction, a plurality of bit lines with each connected to a respective column of the memory cells along a column direction; a column decoder connected to the bit lines; a plurality of sense amplifiers connected to the column decoder; and a plurality of sense amplifier control circuits. Each of the sense amplifiers is connected to a unique one of the sense amplifier control circuits. Each of the sense amplifier control circuits includes a current detector circuit for detecting a sensing current, a current booster circuit for boosting the sensing current, and a timer circuit for providing a delayed trigger for a respective one of the sense amplifiers connected thereto.

Locally timed sensing of memory device

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

Asynchronous/synchronous interface

The present invention is directed to a memory circuitry that includes a magnetic memory element and a selector coupled in series between a first conductive line and a second conductive line; a current detector coupled to the second conductive line; and a means for supplying a sufficiently high voltage to the first conductive line for turning on the selector. When the selector turns on, the current detector detects a current flowing across the selector and effectuates a current limiter to reduce the current while maintaining the selector on. The memory circuitry may be operated by applying a sufficiently high voltage to the first conductive line for turning on the selector; reducing a current flowing through the selector while maintaining the sufficiently high voltage on the first conductive line; and determining a resistance state of the magnetic memory element.

Magnetic memory and method for using the same

The present invention is directed to a method for sensing the resistance state of a memory cell, which includes a memory element and a two-terminal selector coupled in series between first and second conductive lines. The method includes the steps of precharging at least the first conductive line to attain a potential drop across the memory cell that is sufficiently large to turn on the two-terminal selector; allowing the voltage of the first conductive line to decay by discharging through the second conductive line; measuring the voltage of the first conductive line after a discharge period to determine the resistance state of the memory cell; concluding that the memory cell is in the high resistance state if the measured voltage is greater than a reference level; and concluding that the memory cell is in the low resistance state if the measured voltage is less than the reference level.

Transient sensing of memory cells

The present invention is directed to a magnetic memory device that emulates DRAM and provides a plug-in or drop-in replacement for DRAM. The memory device includes one or more magnetic memory banks for storing data; a controller configured to issue a dormant write command upon receiving a refresh command for recharging DRAM capacitors; and a memory cache for storing temporary data and configured to save the temporary data to the one or more magnetic memory banks upon receiving the dormant write command from the controller. The memory device may be compliant with at least one version of low power DDR (LPDDR) Specification or at least one version of DDR SDRAM Specification.

Memory device for emulating dynamic Random access memory (DRAM)

Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.

Apparatuses and methods for a memory die architecture including an interface memory

A method and apparatus that controls a peak-current condition in a multi-die memory, such as a solid-state drive, by determining by at least one die of the multi-die memory whether a subsequent memory operation is a high-current memory operation, such as an operation to enable a charge pump of the die, an operation to charge a bit line of the die, or a program/erase loop operation, or a combination thereof. The die enters a suspended-operation mode if the subsequent memory operation is determined to be a high current memory operation. Operation is resumed by the die in response to a resume operation event, such as, but not limited to, a command specifically address to the die, an indication from another die that a high-current memory operation is complete. Once operation is resumed, the die performs the high-current memory operation.

Auto-suspend and auto-resume operations for a multi-die NAND memory device to reduce peak power consumption

Described embodiments include logical units within a memory device with control circuitry configured to assign a logical unit address to the logical unit. Apparatus including a plurality of the logical units arranged in a daisy chain configuration and methods of assigning logical unit addresses to the logical units are also disclosed.

Logical unit address assignment

Methods and apparatuses for an enhanced block copy. One embodiment is reading data from a source block located in a first portion of the memory device, and programming the data to a target block located in a second portion of the memory device. The first and second portions are communicatively coupled by data lines extending across the portions. The data lines are communicatively uncoupled between the first and second portions for at least one of the reading and programming acts.

Enhanced block copy

Memory devices and methods facilitate handling of data received by a memory device through the use of data grouping and assignment of data validity status values to grouped data. For example, data is received and delineated into one or more data groups and a data validity status is associated with each data group. Data groups having a valid status are latched into one or more cache registers for storage in an array of memory cells wherein data groups comprising an invalid status are rejected by the one or more cache registers.

Growing community of inventors

Cupertino, CA, United States of America

Dean K Nobunaga