Intel Corporation

Dean J Grannes

Stefan Rusu

Gary Leonard Woods

Harry Muljono

Jeremy A Rowlette

Travis M Eiles

Jason A Gayman

Harjinder Singh

Steven G Seidel

A circuit for sensing on-die temperature at multiple locations using a minimum number of pins is described. Thermal diodes coupled to pins are placed on a die to measure the temperature at various die locations. Voltage is applied to the pins to determine the temperature at each given diode location. The polarity of the voltage applied across the pins determines what diodes are selected for measurement.

Circuit for sensing on-die temperature at multiple locations

Time-correlated photon counting is used to measure integrated circuit (IC) performance related to signal jitter (such as clock jitter) in a manner that is non-invasive to the circuit or node of interest. The signal jitter is measured by counting photon emissions at various nodes of interest across a controlled collapse chip connect (C4) mounted die, without interfering with the normal operation of the circuit of interest. This increases the precision and accuracy of the measurement of signal jitter significantly, since small amounts of phase noise on a particular clock signal edge can be detected. The emitted photons can be detected and subsequently correlated to a precise time base to obtain a statistical spread of switching events in time. The range of the photon distribution can be used to reliably determine safe and reasonable timing guard bands for clock and data paths in an IC.

Method and apparatus to measure statistical variation of electrical signal phase in integrated circuits using time-correlated photon counting

A method is provided for manufacturing a die. A supply voltage is provided to a power plane of a selected integrated circuit, formed in and on a semiconductor substrate, having a selected design, so that a respective test current flows through a plurality of test elements, of the selected integrated circuit, each being connected to a respective test point on the power plane, the test points being spaced from one another. A magnitude of each respective test current is detected. A respective test voltage is calculated at each respective test point utilizing the respective magnitude of the respective test current flowing through the respective test element connected to a respective test point. The respective test voltages are utilized to determine at which ones of the test points the respective test voltages are more than a predetermined maximum below a supply voltage. The electric design is altered to an altered electric design if any of the test voltages are below a predetermined minimum below the supply voltage. An integrated circuit having the altered design is then manufactured on another semiconductor substrate.

Semiconductor die manufacture method to limit a voltage drop on a power plane thereof by noninvasively measuring voltages on a power plane

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Fremont, CA, United States of America

Dean J Grannes