Motorola Corporation

Freescale Semiconductor,inc.

Motorlola, Inc.

Dean J Denning

Sam S Garcia

Chitra K Subramanian

Olubunmi O Adetutu

James D Hayden

Rama I Hegde

Robert W Fiordalice

Kurt H Junker

Gregory S Spencer

Arkalgud R Sitaram

John C Arnold

Valli Arunachalam

Jiming Zhang

Gerald A Martin

Philip J Tobin

Jon T Fitch

Peter L G Ventzek

Carlos A Mazure

Scott K Pozder

Bradley Paul Smith

Matthew Thomas Herrick

Cindy Reidsema Simpson

Jeffrey L Klein

Ajay Jain

Ramnath Venkatraman

Brian George Anthony

Phillip E Crabtree

Cristiano Capasso

Scott C Bolton

Gregor Braeckelmann

Gregory Norman Hamilton

Peter Lowell Ventzek

Richard E Martin

Daniel J Loop

Philip E Crabtree

Md Rabiul Islam

A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.

Method of making a die with recessed aluminum die pads

A process for manufacturing semiconductors uses an enclosure ( ) having an interior surface-that is intentionally-roughened by spraying quartz ( ) onto the interior surface. The sprayed quartz ( ) creates additional surface area for the purpose of trapping or capturing etched material in the enclosure during the process. The roughness of the interior surface is not significantly reduced during the semiconductor processing so that only chemical cleaning is required to maintain the interior surface for long-term use.

Method for processing semiconductor wafers in an enclosure with a treated interior surface

A method and an apparatus for forming a layer on a substrate are disclosed. In accordance with one embodiment, a substrate ( ) is placed into a chamber ( ) that includes a coil ( ) and a shield ( ) wherein the coil and the shield are electrically isolated by an isolation/support member ( ) having a first surface ( ) that is substantially contiguous with a surface of the coil and having a second surface ( ) that is substantially contiguous with a surface of the shield. A layer ( ) is then deposited onto the substrate ( ).

Method and apparatus for forming a layer on a substrate

A method for depositing a first metal layer such as tantalum or copper on a patterned semiconductor wafer using a metal sputtering tool that typically includes an electrically biased wafer chuck is disclosed. Initially, a first test wafer is placed on the wafer chuck and a first test layer of materials is deposited on the first test wafer. During the deposition of the first test layer on the first test wafer, the wafer receives the electrical bias at a first level. A second test wafer is then placed on the wafer chuck and a second test layer of material is deposited with the second wafer receiving a second level of electrical bias. The difference in thickness between the first layer and the second layer is then determined. If the difference in thickness is within a predetermined range, the metal sputtering chamber is qualified to deposit a production layer on a production semiconductor wafer.

Percent backsputtering as a control parameter for metallization

A method for forming an improved copper inlaid interconnect (FIG. ) begins by performing an RF preclean operation ( ) on the inlaid structure in a chamber ( ). The RF preclean rounds corners ( and ) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces ( ). A tantalum barrier ( ) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer ( ), a copper seed layer ( ) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp ( ) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.

Method of forming a semiconductor device barrier layer

The formation of an adhesion/interlayer region (,) of a semiconductor substrate device (,) before barrier layer (,) deposition provides improved adhesion of the barrier layer (,) to the underlying dielectric (,) and increases strength to the next interconnect layer without altering the function of the barrier layer (,) to limit Cu diffusion into the dielectric substrate (,). The adhesion/interlayer region (,) is formed in an inlaid structure (,) of a semiconductor wafer. The inlaid structure (,) is connected to upper or lower metal layers through vias in the dielectric layer (,) to a copper layer. The adhesion/interlayer region is formed by flowing a treating gas in a glow discharge process of the dielectric substrate in a chamber either attached or separated from the barrier deposition chamber (,). The barrier layer (,) and the adhesion/interlayer region (,) can be formed in this inlaid structure (,) of a semiconductor wafer. The treating gas (,) can be nitrogen, hydrogen, gases containing carbon atoms, or some other suitable gas.

Semiconductor device adhesive layer structure and process for forming structure

An interconnect (,) is formed overlying a substrate (,). In one embodiment, an adhesion/barrier layer (,), a copper-alloy seed layer (,), and a copper film (,) are deposited overlying the substrate (,), and the substrate (,) is annealed. In an alternate embodiment, a copper film is deposited over the substrate, and the copper film is annealed. In yet another embodiment, an adhesion/barrier layer (,), a seed layer (,), a conductive film (,), and a copper-alloy capping film (,) are deposited over the substrate (,) to form an interconnect (,). The deposition and annealing steps can be performed on a common processing platform.

Method for forming a semiconductor device

A method for insitu performing a cleaning operation along with a physical sputtering operation begins by placing a wafer (,) into a chamber (,). A plasma (,) is generated within the chamber (,) using an inert, noble, or reducing gas. The gas is ionized to form ions (,) within the plasma (,). Power is provided to various components (,and,) within the chamber (,) to ensure that the ions (,) are accelerated towards the wafer (,) during first stages of wafer processing. This acceleration of the ions (,) towards the wafer (,) will clean a surface of the wafer (,). Following this cleaning operation, power supplied within the chamber (,) is altered to accelerate the ions (,) into a reverse direction so that the ions (,) impact a sputter target (,). Due to ionic bombardment of the target (,), a material is sputtered onto a clean surface of the wafer (,) in an insitu manner.

Inert plasma gas surface cleaning process performed insitu with physical vapor deposition (PVD) of a layer of material

A method and an apparatus for forming a layer on a substrate are disclosed. In accordance with one embodiment, a substrate (901) is placed into a chamber (30) that includes a coil (16) and a shield (14) wherein the coil and the shield are electrically isolated by an isolation/support member (32) having a first surface (321) that is substantially contiguous with a surface of the coil and having a second surface (322) that is substantially contiguous with a surface of the shield. A layer (1002, 1102) is then deposited onto the substrate (901).

A A method for forming an improved copper barrier layer begins by providing a silicon-containing layer (10). A physical vapor deposition process is then used to form a thin tantalum nitride amorphous layer (12). A thin amorphous titanium nitride layer (14) is then deposited over the amorphous tantalum nitride layer. A collective thickness of the tantalum nitride and titanium nitride layers 12 and 14 is roughly 400 angstroms or less. A copper material 16 is then deposited on top of the amorphous titanium nitride wherein the composite tantalum nitride layer 12 and titanium nitride layer 14 effectively prevents copper from diffusion from the layer 16 to the layer 10.

Method for forming a conductive structure having a composite or

A metal-semiconductor layer (26) is formed over an insulating layer (20) such that the metal-semiconductor layer (26) is graded to have varying amounts of the semiconductor and metal throughout the layer. In one embodiment, the metal-semiconductor layer (26) has relatively higher silicon content near the layer's lower and upper surfaces. At the midpoint, the layer is close to stoichiometric tungsten silicide. In another embodiment, a metal-semiconductor-nitrogen layer is formed having nitrogen nearer the lower surface and essentially no nitrogen near the upper surface. The layer (26) can be formed using chemical vapor deposition or sputtering.

Process for forming a semiconductor device

A semiconductor device comprises a substrate (100), first conductive film (22 and 32) over the substrate (100), and a second conductive film (54 and 64) over the first conductive film (22 and 32). The first conductive film includes a refractory metal and nitrogen. The first conductive film has a first portion (22) that lies closer to the substrate and a second portion (32) that lies further from the substrate. The nitrogen percentage for the second portion (32) is lower than the nitrogen atomic percentage for the first portion (22). The second conductive film (54 and 64) includes mostly copper. The combination of portions (22 and 32) within the first conductive film provides a good diffusion barrier (first portion) and has good adhesion (second portion) with the second conductive film (54 and 64).

A semiconductor device (10) is formed having an SRAM array with a plurality of SRAM cells. In forming the access and latch transistors, two different gate electrode compositions are used to form the access and latch transistors. More specifically, a dielectric layer (22) is formed between two conductive layers (26 and 28) within the gate electrode (52) for the access transistors while the dielectric layer is not formed between the two conductive layers (26 and 28) for the latch transistors. This structure allows an increase in the beta ratio for the SRAM cell thereby making a more stable SRAM cell without having to use diffused resistors between the access transistors in storage nodes or by having to form a differential thickness between the gate dielectric layers for the latch transistors and the access transistors.

Process for forming a semiconductor device and a static-random-access

A ramp activated low temperature quality epitaxial growth process. A substrate is pre-conditioned and a passivation layer overlying the substrate surface is formed. The substrate is introduced into a process chamber having a controlled temperature. A process chamber purge technique is used to remove oxygen and contaminants from the process chamber before epitaxial growth begins. A process gas, which has an epitaxial growth species, a process chamber purging species and other possible species, is introduced into the process chamber at a low temperature. The process gas and the passivation layer keep the process chamber environment and the substrate surface free from contamination and free from native oxide growth before and, in some cases, during epitaxial growth. The process chamber temperature is gradually elevated to initiate a quality epitaxial growth by starting growth relative to decomposition of the passivation layer.

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Del Valle, TX, United States of America

Dean J Denning