Micron Technology Incorporated

Foundry Networks, Inc.

Chiaro Networks Ltd

Dean E Walker

Tony M Brewer

Chris Baronne

Harold Wallace Dozier

Harry C Blackmon

Thomas C McDermott, Iii

Christopher A Baronne

Bryan D Hornung

David M Patrick

John Amelio

Steven Jeffrey Wallach

Gregory S Palmer

Jim Kleiner

Keith W Shaw

David Traylor

Lou Yeh

Chris Davies

John D Leidel

Michael Grassi

Joe Bolding

William D O'Leary

Kevin R Wadleigh

System and techniques for host-preferred memory operation are described herein. At a memory-side cache of a memory device that includes accelerator hardware, a first memory operation can be received from a host. A determination that the first memory operation corresponds to a cache set based on an address of the first memory operation is made. A second memory operation can be received from the accelerator hardware. Another determination can be made that the second memory operation corresponds to the cache set. Here, the first memory operation can be enqueued in a host queue of the cache set and the second memory operation can be enqueued in an internal request queue of the cache set. The first memory operation and the second memory operation can be executed as each is dequeued.

Host-preferred memory operation

System and techniques for variable execution time atomic operations are described herein. When an atomic operation for a memory device is received, the run length of the operation is measured. If the run length is beyond a threshold, a cache line for the operation is locked while the operation runs. A result of the operation is queued until it can be written to the cache line. At that point, the cache line is unlocked.

Variable execution time atomic operations

System and techniques for recall pending cache line eviction are described herein. A queue that includes a deferred memory request is kept for a cache line. Metadata for the queue is stored in a cache line tag. When a recall is needed, the metadata is written from the tag to a first recall storage, referenced by a memory request ID. After the recall request is transmitted, the memory request ID is written to a second recall storage referenced by the message ID of the recall request. Upon receipt of a response to the recall request, the queue for the cache line can be restored by using the message ID in the response to lookup the memory request ID from the second recall storage, then using the memory request ID to lookup the metadata from the first recall storage, and then writing the metadata into the tag for the cache line.

Recall pending cache line eviction

Devices and techniques for thread replay to preserve state in a barrel processor are described herein. An apparatus includes a barrel processor, which includes a temporary memory; and a thread scheduling circuitry; wherein the barrel processor is configured to perform operations through use of the thread scheduling circuitry, the operations including those to: schedule a current thread to place into a pipeline for the barrel processor on a clock cycle, the barrel processor to schedule threads on each clock cycle; store the current thread in the temporary memory; detect that no thread is available on a clock cycle subsequent to the cycle that the current thread is scheduled; and in response to detecting that no thread is available on the subsequent clock cycle, repeat scheduling the current thread based on the contents of the temporary memory.

Thread replay to preserve state in a barrel processor

A method includes setting an order of input-output channels of a column of a first chiplet of multiple chiplets of a chiplet-based system, wherein one or more of the multiple chiplets include field-configurable input-output channels arranged at a periphery of the chiplets; and programming a second chiplet of the multiple chiplets to change an order of input-output channels of a column of the second chiplet to match the order of input-output channels of the column of the first chiplet.

Method for configuring multiple input-output channels

Devices and techniques for sharing thread memory in a barrel processor via scheduling are described herein. An apparatus includes a barrel processor, which includes thread scheduling circuitry, where the barrel processor is configured to perform operations through use of the thread scheduling circuitry, the operations including those to: place a thread to be scheduled in one of two groups: a first group and a second group, wherein the first group is associated with a first processor storage device, and the second group is associated with a second processor storage device; and schedule a current thread to place into a pipeline for the barrel processor, the scheduling performed by alternating between threads in the first group and threads in the second group.

Thread scheduling control and memory splitting in a barrel processor

System and techniques for silent cache line eviction are described herein. A memory device receives a memory operation from a host. The memory operation establishes data and metadata in a cache line of the memory device upon receipt. The metadata is stored in a memory element that corresponds to the cache line. Later, an eviction trigger to evict the cache line is identified. Then, in response to the eviction trigger, current metadata of the cache line is compared with the metadata in the memory element to determine whether the metadata has changed. the cache line can be evicted without writing to backing memory in response to the metadata being unchanged.

Silent cache line eviction

System and techniques for synchronized request handling at a memory device are described herein. A request is received at the memory device. Here, the request indicates a memory address corresponding to a set of cache lines and a single cache line in the set of cache lines. The memory device maintains a deferred list for the set of cache lines and a set of lists with each member of the set of lists corresponding to one cache line in the set of cache lines. The memory device tests the deferred list to determine that the deferred list is not empty and places the request in the deferred list.

Synchronized request handling at a memory device

Devices and techniques to reschedule a memory request that has failed when a thread is executing in a processor are described herein. When a memory request for a thread is denied at a point in the execution pipeline of the processor beyond a thread rescheduling point, the thread can be placed into a memory response path of the processor. An indicator that a register write-back will not occur for the thread can also be provided. Then, the thread can be rescheduled with other threads in the memory response path.

Rescheduling a failed memory request in a processor

System and techniques for evicting a cache line with pending control request are described herein. A memory request—that includes an address corresponding to a set of cache lines—can be received. A determination can be made that a cache line of the set of cache lines will be evicted to process the memory request. Another determination can be made that a control request has been made to a host from the memory device and that the control request pending when it is determined that the cache line will be evicted. Here, a counter corresponding to the set of cache lines can be incremented (e.g., by one) to track the pending control request in face of eviction. Then, the cache line can be evicted.

Evicting a cache line with pending control request

Systems and techniques for a memory-side cache directory-based request queue are described herein. A memory request is received at an interface of a memory device. One or more fields of the memory request are written into an entry of a directory data structure. The identifier of the entry is pushed onto a queue. To perform the memory request, the identifier is popped off of the queue and a field of the memory request is retrieved from the entry of the directory data structure using the identifier. Then, a process on the memory request can be performed using the field retrieved from the entry of the directory data structure.

Memory-side cache directory-based request queue

To achieve low-latency register error correction, a register can be read as part of an instruction when that instruction is the currently executing instruction in a processor. A correctable error in data produced from reading the register can be detected. In response to detecting the correctable error, the currently executing instruction in the processor can be changed into a register update instruction that is executed to overwrite the data in the register with corrected data. Then, the original (e.g., unchanged) instruction can be rescheduled.

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Allen, TX, United States of America

Dean E Walker