Advanced Micro Devices Corporation

Ati Technologies Ulc

Dean E Gonzales

Gerald Robert Talbot

Milam Paraschou

David Andrew Roberts

Jeffrey Cooper

Pradeep Jayaraman

Edoardo Prete

Prasant Kumar Vallur

Ramon Mangaser

Rahul Agarwal

Srikanth Reddy Gruddanti

Michael J Tresidder

Krishna Reddy Mudimela Venkata

Thomas H Likens, Iii

Chad S Gallun

Balwinder Singh

David H Mcintyre

Xuan Chen

Alushulla Jack Ambundo

Mark Chirachanchai

A chip for wafer-level testing of fanout chiplet, including: a die; a carrier substrate; a plurality of redistribution layers applied to the carrier substrate; and one or more first conductive pathways in the plurality of redistribution layers, wherein the one or more first conductive pathways each comprise a first end coupled to a corresponding input/output connection point of the die and a second end coupled to a corresponding probing site, wherein the one or more first conductive pathways are not routed through the carrier substrate.

Wafer-level testing of fanout chiplets

Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. In order to better handle noise issues when using single-ended signaling, one or more of the receivers include equalization circuitry and termination circuitry. The termination circuitry prevents reflection on a corresponding transmission line ending at a corresponding receiver. The equalization circuitry uses a bridged T-coil circuit to provide continuous time linear equalization (CTLE) with no feedback loop. The equalization circuitry performs equalization by providing a high-pass filter that offsets the low-pass characteristics of a corresponding transmission line. A comparator of the receiver receives the input signal and compares it to a reference voltage. The placement of the comparator and the ratio of the inductances of the inductors of the bridged T-coil circuit are based on whether the receiver includes self-diagnostic circuitry.

Receiver equalization circuitry using variable termination and T-coil

A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.

Skew matching in a die-to-die interface

Techniques are provided herein for pre-emptively reinforcing one or more buses of a computing device against the effects of signal noise that could cause a reduction in signal integrity. The techniques generally include detecting an event (or 'trigger') that would tend to indicate that a reduction in signal integrity will occur, examining a reinforcement action policy and system status to determine what reinforcement action to take, and performing the reinforcement action.

Preemptive signal integrity control

Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

Pseudo differential receiving mechanism for single-ended signaling

Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A receiver includes multiple series inductors moved from a signal path to sampling circuitry to a termination path used for impedance matching. The removed direct current (DC) resistances of the inductors in the signal path reduces signal attenuation. The termination path has alternating current (AC) reactances of the inductors, which provide a frequency-dependent termination impedance. This termination impedance provides a positive reflection coefficient for high operating frequencies, which boosts the input signal being received by the sampling circuitry.

Low loss T-coil configuration with frequency boost for an analog receiver front end

An electronic device includes a first integrated circuit chip including a processing functional block, and a second integrated circuit chip including an input-output (IO) functional block. The IO functional block performs one or more IO processing operations on behalf of the processing functional block in the first integrated circuit chip. The first integrated circuit chip lacks at least some elements of the IO functional block, so that the processing functional block is unable to perform corresponding IO operations without the IO functional block.

Input-output processing on a remote integrated circuit chip

Systems, apparatuses, and methods for implementing a negative resistance circuit for bandwidth extension are disclosed. Within a feedback path of a differential signal path, capacitors are placed on the inputs and outputs of a fully differential amplifier connecting to the differential signal path. In one embodiment, a circuit includes a fully differential amplifier and four capacitors. A first capacitor is coupled between a first signal path and a non-inverting input terminal of the amplifier and a second capacitor is coupled between the first signal path and a non-inverting output terminal of the amplifier. A third capacitor is coupled between a second signal path and an inverting input terminal of the amplifier and a fourth capacitor is coupled between the second signal path and an inverting output terminal of the amplifier. The first and second signal paths carry a differential signal.

Growing community of inventors

Fort Collins, CO, United States of America

Dean E Gonzales