Intel Corporation

Other

Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Institute for the Development of Emerging Architectures, L.l.c.

Dean A Mulla

Gregory Scott Mathews

Krishnakanth Venkata Sistla

Sorin Iacobovici

Terry L Lyon

John Wai Cheong Fu

Vivek Garg

Reid James Riedlinger

Alexander Gendler

Nhon Toai Quach

Stuart E Sailer

John Wai Fu

Tom Grutkowski

Keith Robert Pflederer

Shawn Kenneth Walker

Thomas Grutkowski

Doron Rajwan

Ganapati Srinivasa

Donald Charles Soltis, Jr

Ashish V Choubal

Tal Kuzi

Jeffrey D Gilbert

Nazar Syed Haider

Ariel Szapiro

Sunny C Huang

Mark Rowland

Jeng-Jye Shaw

Jeen Miin

Nir Tell

Suresh Doraiswamy

William G Sicaras

Daming Jin

Mohan J Kumar

Andrew J Herdrich

Alan Hersh Karp

Rahul Khanna

Ankush Varma

Dale Calvin Morris

Douglas John Cutter

James B Crossland

Shivnandan D Kaushik

Achmed Rumi Zahir

Eric J DeHaemer

Ashish Gupta

Lily Pao Looi

Bahaa Fahim

Jerome C Huck

Larisa Novakovsky

David Allen Fotland

Alberto J Munoz

Glenn T Colon-Bonet

Nikhil Gupta

Guy G Sotomayor

Arvind Raman

Riccardo Mariani

Eric R DeLano

Allan Douglas Knies

Daniel G Borkowski

Erik Hallnor

James O Hays

Ripan Das

Rahul Agrawal

Yogesh Bansal

Adwait Purandare

Amy L O'Donnell

Suresh Chemudupati

Kimberly C Weier

Len J Schultz

Aman Sewani

Eric Dehaemer

James S Finnell

Lakshmikant Mamileti

Allen W Chu

Rupal Parikh

Nilanjan Palit

Manev Luthra

Pavithra Sampath

Victor J Wu

Robert Steven Gottlieb

Valentin Anders

Ujjwal Gupta

John W C Fu

Nikethan Shivanand Baligar

Stanley Chen

Jim Hays

Stanley Steven Kulick

Stephen Wang

Dorit Shapira

Shruthi Venugopal

Phani Kumar Kandula

Michael Tulanowski

Donald C Soltis

Timothy Yee-Kwong Kam

Stephen Paul Haake

Reid J Reidlinger

Don R Weiss

Joe R Butler

Erik G Hallnor

Victor Wu

Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Hierarchical power management apparatus and method

A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.

Instruction and logic for parallel multi-step power management flow

Methods and apparatus relating to provision of core tightly coupled lockstep for high functional safety are described. In an embodiment, a master core, coupled to a slave core, executes one or more operations to support Advanced Driver Assistance Systems (ADA) or autonomous driving. The master core and the slave core receive the same input signal and core tightly couple logic causes generation of a signal in response to comparison of a first output from the master core and a second output from the slave core. The generated signal causes an interruption of the one or more operations in response to a mismatch between the first output and the second output. Other embodiments are also disclosed and claimed.

Core tightly coupled lockstep for high functional safety

In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.

Controlling telemetry data communication in a processor

Systems, methods, and devices are disclosed for mitigating voltage droop in a computing device. An example apparatus includes a plurality of threshold registers to store respective voltage droop thresholds, and an interface to receive a license grant message indicating a license mode for a processor core or domain. The license mode corresponds to a selected set of execution units in the processor core or domain. The apparatus also includes a voltage droop correction module to, based on the license mode indicated in the license grant message, select one of the voltage droop thresholds from the plurality of voltage droop registers, and compare a voltage droop in the processor core or domain with the selected voltage droop threshold. Based on the comparison, the apparatus triggers a voltage droop correction process.

Systems and methods for core droop mitigation based on license state

Systems and methods may provide for determining, in a first domain that manages a state of a second domain, that the second domain is in the state and determining, in the first domain, that a periodic action has been scheduled to occur in the second domain while the second domain is in the state. Additionally, the periodic action may be documented as a missed event with respect to the second domain. In one example, documenting the periodic action as a missed event includes incrementing a missed event counter.

Tracking missed periodic actions across state domains

In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.

Masking a power state of a core of a processor

In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.

Dynamically adjusting power of non-core processor circuitry including buffer circuitry

Embodiments of the invention are generally directed to apparatuses, methods, and systems for a computing system feature activation mechanism. In an embodiment, a computing system receives a remotely generated feature activation information. The computing system compares the remotely generated feature activation information with a built-in feature activation mechanism. In an embodiment, a feature of the computing system is activated if the remotely generated feature activation information matches the built-in feature activation mechanism. Other embodiments are described and claimed.

Computing system feature activation mechanism

Atomic sixteen-byte memory accesses are provided in a 64-bit system in which eight of the bytes are stored in a 64-bit general-purpose register and eight of the bytes are stored in a 64-bit special-purpose register. A 16-byte load instruction transfers the low eight bytes to an explicitly specified general-purpose register, while the high eight bytes are transferred to the special-purpose register. Likewise, a 16-byte store instruction transfers data from a general-purpose register and the special-purpose register. Also provided is an 8-byte compare conditioning a 16-byte exchange semaphore instruction that can be used to accelerate algorithms that use multiple processors to simultaneously read and update large databases.

Superword memory-access instructions for data processor

In some embodiments, an apparatus includes a processor, an expander memory bridge location, a memory coupled to the expander memory bridge location, and a bus controller including intercept logic to intercept and block communication from the processor to the expander memory bridge location and to emulate an expander memory bridge. In some embodiments, a method includes intercepting and blocking a status request to a device, regardless of whether the device is installed, and responding to the status request.

Apparatus, system, and method to enable transparent memory hot plug/remove

A computer data signal comprises a first code group and a second code group. The first code group has a first symbol and an error detection code for the first symbol. The second code group has a second symbol different from the first symbol and an error correction code. The error correction code provides error correction for a third symbol that includes the first symbol and the second symbol.

Combined tag and data ECC for enhanced soft error recovery from cache tag errors

A control hub includes a first interface and a second interface to transfer data. The first interface connects to a first bus. The second interface connects to a peripheral bus. The control hub receives configuration address and configuration data during a configuration access. The control hub transfers the configuration data between the first interface and the second interface without transferring the configuration data to a configuration data register. The control hub further includes other interfaces to allow access to peripheral devices for system management and testing purposes.

Method and apparatus for configuring communication between devices in a computer system

Growing community of inventors

Fort Collins, CO, United States of America

Dean A Mulla