Advanced Micro Devices Corporation

International Business Machines Corporation

Sun Microsystems, Inc.

Dean A Liberty

Vilas K Sridharan

Magiting M Talisayon

Srikanth Masanam

Vydhyanathan Kalyanasundharam

David S Christie

Michael T Clark

Amit P Apte

Andrew E Phelps

David L Isaman

Kirk D Pospesel

Ross Voigt La Fetra

Jelena Ilic

Cristian Constantinescu

James R Williamson

Thomas F Dubois

An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). The first partition includes a host processor that executes an exception handler for managing reported errors. A message converter unit of the second partition assists in generating messages based on detected errors in the second partition. The message converter unit receives requests from hardware components of the second partition for handling errors and translates MCA addresses between the first partition and the second partition. To support the message converter unit, during an earlier bootup operation, the second partition communicates the hardware topology of the second partition to the host processor, and the host processor sends address translation information.

Remote scalable machine check architecture

An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). When a host processor in the first partition detects an error that requires information from processor cores of the second partition, the host processor generates an access request with a target address pointing to a storage location in a memory of the second partition, not the first partition. When the host processor receives the requested error log information from the second partition, the host processor completes processing of the error. To support the host processor in generating the target address for the access request, during an earlier bootup operation, the second partition communicates the hardware topology of the second partition to the host processor.

Scalable machine check architecture

Systems, apparatuses, and methods for implementing a hardware enforcement mechanism to enable platform-specific firmware visibility into an error state ahead of the operating system are disclosed. A system includes at least one or more processor cores, control logic, a plurality of registers, platform-specific firmware, and an operating system (OS). The control logic allows the platform-specific firmware to decide if and when the error state is visible to the OS. In some cases, the platform-specific firmware blocks the OS from accessing the error state. In other cases, the platform-specific firmware allows the OS to access the error state such as when the OS needs to unmap a page. The control logic enables the platform-specific firmware, rather than the OS, to make decisions about the replacement of faulty components in the system.

Platform first error handling

A method and device are described for encoding erroneous data in an error correction code (ECC) protected memory. In one embodiment, incoming data including a plurality of data symbols and a data integrity marker is received. At least one extra symbol is used to mark the incoming data as error-free data or erroneous data (i.e., poison) based on the data integrity marker. ECC may be created to protect the data symbols. The ECC may include a plurality of check symbols, a plurality of unused symbols and the at least one extra symbol. In another embodiment, an error marker may be propagated from a single ECC word to all ECC words of data block (e.g., a cache line, a page, and the like) to prevent errors due to corruption of the error marker caused by faulty memory in the erroneous ECC word.

Method and apparatus for encoding erroneous data in an error correction code protected memory

An electronic system includes a counter and a first component. The first component includes a reset input configured to receive a reset event, an interface to a communications interface coupleable to a second component, an error detection module configured to initiate the counter in response to detecting an error in a first communication from the second component, and an event logging module. The event logging module is configured to store a first indicator representative of the counter value of the counter in response to receiving the reset event via the reset input and configured to store a second indicator representative of the error at the communications interface. The counter is initiated at the first component in response to detecting an error in a first communication from the second component. A counter value of the counter is determined in response to detecting a reset event at the first component subsequent to detecting the error in the first communication. A first indicator representative of the counter value and a second indicator representative of the error in the first communication is stored at the electronic system.

Method and system for identifying communication errors resulting from reset skew

A method of utilizing timestamps for the global ordering of event information, particularly hardware error reporting, is disclosed. Locally generated time stamps are associated with hardware errors or other events. The timestamps form the basis for the global ordering of event information. The timestamps are normalized, either through a pre-synchronization process with a common time, or through the use of offsets maintained either locally near system chips or by the system processor. Once normalized, the timestamps can be compared to determine a first occurring event among multiple reported events.

System and method for determining a global ordering of events using timestamps

A method, an apparatus and computer readable medium for simultaneous communication over a bus in a master/slave agent network topology. Each communication agent on the network is either a master agent or slave agent with an input and an output. In one embodiment, the input and the output are latches. The method permits the number of tokens on the ring to be equal to up to one less than the total number of agents on the ring.

Method and system for simultaneous management of multiple tokens on a communication ring

A hybrid non-uniform-memory-architecture/simple-cache-only-memory-architecture (NUMA/S-COMA) memory system and method are described useful in association with a computer system having a plurality of nodes coupled to each other. The plurality of nodes include NUMA memory which are configured to store data lines. The NUMA memories include a NUMA coherence subsystem for coordinating transfer of data between the nodes. At least one S-COMA cache is provided on at least one node of the computer system. The at least one S-COMA cache is configured to employ the NUMA coherence subsystem in sending data communication to or receiving data communication from another node of the plurality of nodes of the computer system. Data stored at another node of the system is accessed using a home node real address as the network address. The home node real address is translated into a local real address at the client node using a boundary function translation table. The NUMA coherence subsystem is employed by the S-COMA cache to provide data reference capture, data movement and coherence mechanisms, thereby avoiding the need for a separate S-COMA coherence mechanism to accomplish these functions.

Growing community of inventors

Nashua, NH, United States of America

Dean A Liberty