United Microelectronics Corp.

De-Yuan Wu

Chih-Cheng Liu

Sun-Chieh Chien

Hsin-Hui Hsu

Yung-Chung Lin

Ling-Hsu Tsang

A memory module stores digital data. The memory module has many memory cells biased by a voltage source. Each memory cell has an access transistor electrically connected to a word line and a bit line for receiving bits from the bit line when the word line turns on the access transistor, a switching circuit electrically connected to the access transistor, and a capacitor electrically connected to the switching circuit. The switching circuit turns on or off according to the bit from the access transistor. The capacitor stores charge supplied by the switching circuit when the switching circuit turns on. The capacitor stores charge supplied by the voltage source when the switching circuit turns off. When the access transistor turns off, the switching circuit or the voltage source provides charge to the capacitor to sustain the voltage level of the capacitor to compensate for charge leakage of the capacitor.

Memory module having a two-transistor memory cell

A SOI DRAM unit comprising a MOS transistor and an improved SOI substrate having a back-gate control. The SOI substrate includes a first insulating layer, a first semiconductor layer having a first conductivity type, a second insulating layer, and a second semiconductor layer having a first conductivity type formed on a substrate. The MOS transistor includes a gate formed on the second semiconductor layer and a source and drain region, having a second conductivity type, formed on either side of the gate in the second semiconductor layer, wherein the source and the drain electrically connects to a bit line and a capacitor, respectively. A first oxidation region is formed in the first semiconductor layer below the source region and a second oxidation region is formed in the first semiconductor layer below the drain region. Both the first oxidation and second oxidation regions are contiguous with the second insulating layer.

SOI device and method of fabrication

The present invention provides a method of planarization for an inter layer dielectric of an EDRAM. The method comprises defining a periphery circuit region and a memory array area on a semiconductor wafer of the EDRAM, and forming a plurality of MOS transistors and capacitors. As well, both a dielectric layer and a photoresist layer are formed on the semiconductor wafer using the layout patterns of a storage node of thecapacitors as a reverse mask to perform an etching process. Consequently, portions of the photoresist layer in the memory array area are removed while simultaneously etching the dielectric layer in the memory array area by a predetermined depth. Finally, a chemical mechanical polishing process is performed on the dielectric layer to planarize the inter layer dielectric of the EDRAM.

ILD planarization method

The present invention provides a method of reducing resistance in an Al-containing conductor. An Al oxide layer is first formed on the surface of an Al-containing conductor followed by the formation of a Ti layer and a barrier layer above the Al oxide layer, respectively. Finally, a W contact plug is formed within the barrier layer. The Al oxide layer functions in preventing a reaction between the Ti layer and the conductor during high temperature formation of the W contact plugs to avoid the influence of resistance in the Al-containing conductor.

Method for reducing resistance in a conductor

A method of fabricating a deep trench capacitor is achieved. A deep trench is formed in a silicon substrate followed by the formation of a buried plate in the silicon substrate beneath the deep trench. A silicon nitride layer is formed on the surface of the deep trench above the buried plate. An oxidation process is performed to simultaneously form a first oxide film on the silicon nitride layer and a second oxide film on the silicon substrate within the deep trench. A doped polysilicon layer is formed in the deep trench with its surface lowered down to the surface of the substrate. Finally, a portion of the second oxide film is removed to expose the substrate in the upper region of the deep trench followed by the filling in of an undoped polysilicon layer into the deep trench to finish the fabrication process of the DRAM deep trench capacitor.

Method of fabricating a deep trench capacitor

A method of fabricating a buried vertical split gate memory cell is disclosed. First, a first trench is created in an SOI substrate for accommodating a floating gate. A second trench, having a smaller width than that of the first trench, is then created at the bottom of the first trench for accommodating a word line/control gate. Simultaneously, a silicon sidewall step structure is produced and functions as a vertical channel of the buried vertical split gate memory cell, wherein the vertical control gate channel length (L,) and the floating gate channel length (L,) is 0.25 micrometers and about 3.5 nm, respectively.

Growing community of inventors

Hsin-Chu, Taiwan

De-Yuan Wu