Taiwan Semiconductor Manufacturing Comp. Ltd.

De-Yuan Lu

Hung-Jui Kuo

Ming-Tan Lee

Tai-Min Chang

Chung-Shi Liu

Chen-Hua Douglas Yu

Hui-Jung Tsai

Hao-Yi Tsai

Tin-Hao Kuo

Wen-Hsiung Lu

Chien Ling Hwang

Ming-Che Ho

Yu-Feng Chen

Cheng-Chung Lin

Po-Yuan Teng

Ying-Jui Huang

Meng-Wei Chou

Tzung-Hui Lee

Bor-Rung Su

Chun-Lei Hsu

Kuo Cheng Lin

Ming-Fa Chen

Chen-Cheng Kuo

Yao-Hwan Kao

Jia-Sheng Lee

A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.

Packages with enlarged through-vias in encapsulant

A photoresist apparatus and a method are provided. The photoresist apparatus includes a pre-baking apparatus. The pre-baking apparatus includes: a hot-plate, a first cover over the hot-plate, a second cover over the first cover, a first heating element extending along a topmost surface of the first cover, and a second heating element extending along a topmost surface of the second cover.

Photoresist system and method

A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.

Semiconductor package and manufacturing method thereof

A semiconductor device and method of making a conductive connector is provided. In an embodiment an opening is formed within a photoresist by adjusting the center point of an in-focus area during the exposure process. Once the photoresist has been developed to form an opening, an after development baking process is utilized to reshape the opening. Once reshaped, a conductive material is formed into the opening to take on the shape of the opening.

Methods of manufacturing semiconductor devices

Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.

Pillar bumps and process for making same

A method of packaging semiconductor dies may include: coupling a first die to a first substrate; forming a plurality of first portions of a plurality of metal pillars on a surface of the first substrate; forming a second portion of the plurality of metal pillars over each of the plurality of first portions of the plurality of metal pillars; forming a protection layer over sidewalls of each of the plurality of first portions and second portions of the plurality of metal pillars; coupling a second die to a second substrate; and coupling the plurality of metal pillars to the second substrate.

Package on package devices and methods of packaging semiconductor dies

Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. In one embodiment, a PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal pillars are coupled to the first packaged die. The metal pillars have a first portion proximate the first packaged die and a second portion disposed over the first portion. Each of the metal pillars is coupled to a solder joint proximate the second packaged die.

Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.

A method and apparatus for adjusting exhaust flow, and the apparatus has a programmable exhaust control regulator generating a first input signal to a motor control circuit, an exhaust flow meter generating a second input signal to the motor control circuit and a motor driven control valve moved to different positions according to the first and second input signals, the control valve being installed in an exhaust portion of the hot plate apparatus.

Growing community of inventors

Taipei, Taiwan

De-Yuan Lu