Taiwan Semiconductor Manufacturing Comp. Ltd.

De-Wei Yu

Chien-Hao Chen

Ziwei Fang

Pin-Ju Liang

Yee-Chia Yeo

Chun Hsiung Tsai

Yu-Lien Huang

Cheng-Po Chau

Chia-Ao Chang

Tsan-Chun Wang

Yun Chen Teng

Yi-Cheng Li

Weng Chang

Liang-Gi Yao

Chih-Tang Peng

Zheng-Yang Pan

Lun-Kuang Tan

Yi-Fan Chen

Ya-Wen Chiu

Sheng-Wen Yu

Hung-Yao Chen

Yi Che Chan

I-Chen Yang

Hsueh-Chang Sung

Pei-Ren Jeng

Tsu-Hsiu Perng

Jei Ming Chen

Chia Ping Lo

Pin-Chu Liang

Shu-Yi Wang

Yen-Ming Chen

Chii-Horng Li

Yung-Cheng Lu

Li-Zhen Yu

Dian-Hau Chen

Hsiang-Ku Shen

Jr-Hung Li

Chi-On Chui

Chien-Tai Chan

Ying-Liang Chuang

Shih-Wei Wang

Bo-Cyuan Lu

Tsung-Chieh Hsiao

Wen-Sheh Huang

Hung-Yi Huang

Min-Hsiu Hung

Yen-Chun Huang

Ming-Feng Hsieh

Chia-Lin Chuang

Jin-Mu Yin

Chun-Cheng Chou

Chia-Ping Lo

Chien-Chia Cheng

In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

Method of manufacturing a semiconductor device and a semiconductor device

A method includes etching a semiconductor substrate to form a trench between a first semiconductor strip and a second semiconductor strip. The first semiconductor strip has a first width at about 5 nm below a top of the first semiconductor strip and a second width at about 60 nm below the top of the first semiconductor strip. The first width is smaller than about 5 nm, and the second width is smaller than about 14.5 nm. The trench is filled with dielectric materials to form an isolation region, which is recessed to have a depth. A top portion of the first semiconductor strip protrudes higher than the isolation region to form a protruding fin. The protruding fin has a height smaller than the depth. A gate stack is formed to extend on a sidewall and a top surface of the protruding fin.

Fin bending reduction through structure design

A method for forming a semiconductor device and a semiconductor device formed by the method are disclosed. In an embodiment, the method includes depositing a dummy dielectric layer on a fin extending from a substrate; depositing a dummy gate seed layer on the dummy dielectric layer; reflowing the dummy gate seed layer; etching the dummy gate seed layer; and selectively depositing a dummy gate material over the dummy gate seed layer, the dummy gate material and the dummy gate seed layer constituting a dummy gate.

Semiconductor device and method

A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.

Method of performing gap filling including filling trenches between dummy gate stacks on semiconductor fins/strips with semiconductor material

A method of forming a semiconductor device includes depositing a film over a dielectric layer. The dielectric layer is over a first fin, a second fin, and within a trench between the first fin and the second fin. The method further includes etching top portions of the film, performing a treatment on the dielectric layer to remove impurities after etching the top portions of the film, and filling the trench over the remaining portions of the film. The treatment includes bombarding the dielectric layer with radicals.

Semiconductor device and method for manufacture

Method of gap filling using conformal deposition-annealing-etching cycle for reducing seam void and bending

Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

Semiconductor device structure with salicide layer and method for forming the same

Embodiments disclosed herein relate generally to forming a structure, e.g., in high aspect ratio trenches. In an embodiment, a method for semiconductor processing is provided. The method includes forming fins on a substrate. Sidewalls of the fins and a bottom surface between the sidewalls of the fins define a trench therebetween. The method includes forming a gate structure over the fins. The gate structure has a sidewall with a defect region formed therein. The method includes forming a filling layer to fill the defect region in the sidewall of the gate structure.

Defect filling in patterned layer

Methods of forming a material layer are provided. The material layer, such as amorphous silicon, may be formed by repeatedly depositing and annealing amorphous silicon. Periodically, an etching process may be performed to widen openings between fins or other topography if necessary. The depositing, annealing, and etching process may be repeated. Subsequently, an additional layer of amorphous silicon may be deposited to a desired thickness.

Method for forming a FinFET structure that prevents or reduces deformation of adjacent fins

Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a cyclic deposition-etch process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes forming a dielectric cap layer on the conformal film. The method includes performing an anneal process on the conformal film.

Cap layer and anneal for gapfill improvement

Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-treatment process. In an embodiment, a method includes subjecting a substrate surface having at least one feature to a film deposition process to form a conformal film over a bottom surface and along sidewall surfaces of the feature, subjecting the substrate surface to a treatment process to form respective halogen surface layers or respective halogen-terminated layers on the conformal film formed at respective upper portions of the sidewall surfaces, and performing sequentially and repeatedly the film deposition process and the treatment process to fill the feature with the film.

Selective silicon growth for gapfill improvement

Growing community of inventors

Ping-Tung, Taiwan

De-Wei Yu