International Business Machines Corporation

De Tran

Donald W Price

Warren W Grunbok

Dale E Pontius

Billy J Knowles

Robert Tamlyn

Yee-Ming Ting

William R Milani

Henry Yeh

Douglas R Moran

A stride enhancer provides high memory bandwidth on strides greater than one and minimizes requests to memory. The basic memory module (BSM) design uses line fetches as the basic cache complex fetch mechanism and allows operation of the BSM to be stride independent. In the preferred implementation, the BSM has two fetch modes; a normal mode and a line fetch mode. In the normal mode, a quadword (QW) is fetched as in the conventional design. In the line fetch mode, all double words (DWs) within the referenced line are returned to the storage control element (SCE) at two DWs per cycle for strides one through eight (twice the conventional bandwidth) or at least one DW per cycle for all other strides (equal to the conventional bandwidth). This is accomplished with two DW busses rather than a single QW bus and by interleaving DW storage locations within the BSM. In line fetch mode for strides one through eight, DWs are read out according to the stride on the two DW busses.

Stride enhancer for high speed memory accesses with line fetching mode

A memory system and a unique memory chip is disclosed wherein multiple islands on a chip can be separately accessed by separate island controllers whereby concurrent use of the several islands or arrays on a chip can be achieved.

Memory system and unique memory chip allowing island interlace

Growing community of inventors

Woodstock, NY, United States of America

De Tran