Qualcomm Incorporated

Fairchild Semiconductor Corporation

Raytheon Company

De Dzwo Hsu

Gilbert Christopher Sih

Mehdi Hamidi Sani

Willard Kraig Bucklen

Yun Du

Chun Yu

Guofang Jiao

Jian Wei

Xufeng Chen

Richard Higgins

Charles E Sakamaki

Szepo Robert Hung

Hsiang-Tsun Li

Stephen A Molloy

Way-Shing Lee

Jentsung Lin

Raghavendra Nagaraj

Eai-Hsin Alfred Kuo

Frederick Alan Williams

Wendy L Liu

A multi-threaded processor is provided, such as a shader processor, having an internal unified memory space that is shared by a plurality of threads and is dynamically assigned to threads as needed. A mapping table that maps virtual registers to available internal addresses in the unified memory space so that thread registers can be stored in contiguous or non-contiguous memory addresses. Dynamic sizing of the virtual registers allows flexible allocation of the unified memory space depending on the type and size of data in a thread register. Yet another feature provides an efficient method for storing graphics data in the unified memory space to improve fetch and store operations from the memory space. In particular, pixel data for four pixels in a thread are stored across four memory devices having independent input/output ports that permit the four pixels to be read in a single clock cycle for processing.

Unified virtual addressed register file

This disclosure describes efficient transformation techniques that can be used in video coding. In particular, intermediate results of computations associated with transformation of a first block of video data are reused in the transformation of a second block of video data. The techniques may be used during a motion estimation process in which video blocks of a search space are transformed, but this disclosure is not necessarily limited in this respect. Pipelining techniques may be used to accelerate the efficient transformation techniques, and transposition memories can be implemented to facilitate efficient pipelining.

Efficient transformation techniques for video coding

A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.

Cached memory system and cache controller for embedded digital signal processor

Caching techniques for storing instructions, constant values, and other types of data for multiple software programs are described. A cache provides storage for multiple programs and is partitioned into multiple tiles. Each tile is assignable to one program. Each program may be assigned any number of tiles based on the program's cache usage, the available tiles, and/or other factors. A cache controller identifies the tiles assigned to the programs and generates cache addresses for accessing the cache. The cache may be partitioned into physical tiles. The cache controller may assign logical tiles to the programs and may map the logical tiles to the physical tiles within the cache. The use of logical and physical tiles may simplify assignment and management of the tiles.

Tiled cache for multiple software programs

A method of changing execution contexts is provided that includes receiving a context selection input. In a first clock phase, the method includes shifting data from a first latch element of a normal execution context to a second latch element of the normal execution context and shifting shadow data from a third latch element of a shadow execution context to a fourth latch element of the shadow execution context. In a second clock phase, the method includes shifting the shadow data of the fourth latch element of the shadow execution context into the first latch element of the normal execution context and shifting the data of the second latch element of the normal execution context into the third latch element of the shadow execution context. In a particular embodiment, the method may include receiving a test mode selection and shifting test data, such as scan test or automatic test pattern generated data, to a test output.

Method and context switch device for implementing design-for-testability functionality of latch-based register files

Automatic white balance of captured images can be performed based on a gray world assumption. One aspect relates to an apparatus comprising a collection module and a processor. The collection module is configured to accumulate (a) red/green and blue/green color ratio values of a plurality of pixels in a captured image for each cluster of a plurality of clusters and (b) a number of pixels having red/green and blue/green color ratios associated with each cluster, the clusters comprising daylight, fluorescent, incandescent, and a outdoor green zone. The processor is configured to determine which cluster has a highest accumulated number of pixels, and use the cluster with the highest accumulated number of pixels to perform white balancing for the captured image.

Automatic white balance statistics collection

DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU configuration, a single-MAC/dual-ALU configuration, or a dual-MAC/dual-ALU configuration. This flexibility allows the DSP to handle various types of signal processing operations and improves utilization of the available hardware. The DSP architectures further includes pipeline registers that break up critical paths and allow operations at a higher clock speed for greater throughput.

Digital signal processors with configurable dual-MAC and dual-ALU

A VGA to analog video converter is useful e.g. for displaying video and/or graphics data from a computer onto a large screen television or television monitor. The RGB video signals output from the personal computer are first converted to digital form. The analog-to-digital converter which does this is clocked by a clock signal generated by a phase-locked loop using the horizontal synchronizing signal from the personal computer. The digital RGB signals are then converted to a YCbCR format. A flicker filter eliminates the flickering appearing on the TV monitor by operating on the luminance (Y) component. The YCbCr signals are encoded into NTSC or PAL Standard, and output in composite analog video or S-VHS format. A color subcarrier synthesizer generates the color subcarrier signal to generate an accurate subcarrier frequency for the video output signals. An analog-to-digital clock phase adjustment is used to ensure that the input RGB signals are sampled at the proper instant by the analog-to-digital converters.

Video signal converter for converting non-interlaced to composite video

Two multiply-accumulate units are coupled together so that the computation (B*C)&plus;(D*E) can be completed in one cycle. An adder ( ) adds together the products of the two multipliers ( ), ( ). The sum is applied to the first accumulator ( ). Preferably, the second product is also applied to the second accumulator ( ), and a multiplexer ( ) applies either a zero or the second product to the adder ( ). If two unrelated computations are to be executed simultaneously, then the zero is applied, and the output of the second accumulator is fed back to the register file (PI ). If a single (B*C)&plus;(D*E) computation is to be executed, then the second product is applied to the adder, and the output of the second accumulator is disregarded.

Digital signal processor with coupled multiply-accumulate units

Method for converting analog video signal to digital video signal

Method and apparatus for video flicker filter

A color subcarrier signal generator for use e.g, in a video converter measures the average error of the horizontal synchronizing signal frequency. The measured error is used as a compensator signal to control a direct digital synthesizer to generate a correct color subcarrier signal. The direct digital frequency synthesizer includes an address generator receiving the error signal and a look up table driven by the address generator.

Video color subcarrier signal generator

A high resolution digital phase detector adapted to receive a threshold value and a sequence of digital samples of a substantially linear portion of an analog video signal. A first output signal is provided when a digital sample is detected as having crossed the threshold value. An interpolation is done between the value of the digital sample to first cross the threshold value and the immediately preceding digital sample on the opposite side of the threshold value. In such manner, the time of the crossing within the sample interval is resolved to a subpixel level. A second output signal represents a fractional phase error between the actual crossing and a desired crossing point within the sample interval. The first and second signals are added in a phase locked loop to adjust the output of a voltage controlled oscillator to be synchronized to the incoming analog video signal in both integer and subpixel phase.

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De Dzwo Hsu