Nxp B.v.

Koninklijke Philips Corporation N.v.

Microchip Technology Inc.

Philips Electronics North America Corporation

Dc Sessions

David R Evoy

Yong Yuenyongsgool

Elie Khoury

John C Ciccone

Carl F Liepold

Dennis Koutsoures

Tim Wilson

Qing He

Ivan Svestka

James Muha

Elie G Khoury

An integrated circuit device has a primary voltage regulator and an ultra-low power secondary voltage regulator. The ultra-low power secondary voltage regulator supplies voltage to certain circuits used for providing data retention and dynamic operation, e.g., a real time clock and calendar (RTCC) when the integrated circuit device is in a low power sleep mode. The primary voltage regulator provides power to these same certain circuits when the integrated circuit is in an operational mode.

Data retention secondary voltage regulator

A novel high-speed phase splitter circuit () and method of operation are disclosed. This high-speed phase splitter () creates a differential rail-to-rail output signal from a single ended input signal, with an inherent low skew and symmetrical output. The circuit () uses a phase splitting input stage () followed by several amplification stages () that are symmetrical and balanced in nature.

High speed rail to rail phase splitter for providing a symmetrical differential output signal having low skew

A communications port is implemented for configuration in direction and arrangement. According to an example embodiment of the present invention, a communications link (), such as a PCI Express type link, is configurable for communicating with devices having different directional and/or polarity configurations. The communications link is configured to match a communications port condition (e.g., a directional and/or polarity condition) of a device () coupled to the communications link. In one instance, the communications link is directionally configurable for reassigning input lanes to output lanes and output lanes to input lanes. With this approach, the communications link can be used to communicate with a variety of devices having varied communication characteristics.

Communications device and method for configuring a communication port depending on a direction condition of a remote device communicatively coupled to the communications port

A novel high speed, &#x3e;1 GHz or 2 Gbits/s, low voltage differential signal (LVDS) driver is disclosed. The LVDS design achieves low power consumption while providing LVDS compliant impedance termination to power supply and ground. An output stage of the LVDS is implemented using a Nmos and a Pmos follower in a push pull configuration. This new design relies first on a follower type of an output stage, which provides the inherent impedance termination, second on an AC, capacitive, coupling and DC restoration to drive output stage gates, and on a low power dummy bias generator that supplies DC restoration voltages. As the supply voltage is lower the thick oxide devices performance suffer, therefore for this new design is mainly implemented with thin oxide devices.

Ultra low power LVDS driver with built in impedance termination to supply and ground rails

A novel high-speed differential receiver is disclosed that provides a new method and apparatus receiving and amplifying a small differential voltage with a rail-to-rail common mode voltage. The receiver output signals are differential signals with low skew and high symmetry. This high-speed differential receiver is based on a common mode voltage normalization, which is based on a differential phase splitting methodology, before the resulting signal is recombined, normalized and amplified. The method involves using a differential signal splitting followed by a common mode voltage normalization stage, then a controlled gain transimpedance amplification, and then amplification using one or two rail to rail amplification stages that are symmetrical and balanced in nature.

High speed differential receiver with rail to rail common mode operation having a symmetrical differential output signal with low skew

In one example embodiment involving a high-speed parallel-data communication from a first module to a second module, a termination circuit is adapted to reduce power consumption at the second module. The termination circuit includes resistive circuits respectively coupled to a plurality of parallel data-carrying lines that form the data bus. The other ends of the resistive circuits are interconnected to provide a reference voltage using the data on the parallel data-carrying lines. Consistent with one embodiment of the present invention, the communication approach uses data sets encoded so that each data set includes the same number of ones and zeroes; in this manner the reference voltage is always at midpoint and useful in providing termination to the data-carrying lines at all times.

Parallel data communication consuming low power

An ESD protection circuit is provided which offers full protection for sub micron CMOS technology integrated circuits that does not have a latchup problem as in silicon controller rectifier circuits. The primary ESD protection transistor within the circuit channeling deleterious ESD currents away from the electrical circuit using snapback conduction while additionally enabling bipolar operation of the electrical circuit.

Polarity reversal tolerant electrical circuit for ESD protection

An approach for impedance matching a transmission line includes using the actual line impedance. According to one example embodiment, the impedance of a line connecting first and second nodes is calibrated by first driving the line to a steady-state voltage using a first current having a magnitude greater than zero, driving the current to a zero magnitude from the first node and therein inducing a voltage transient. The resultant voltage level on the line at the first node is then measured and analyzed relative to a reference voltage. The result of the comparison is then used to adjust the conductance at the second node.

Line impedance calibration using actual impedance determination

A signal converter is provided for converting multiple level encoded digital signals into a binary equivalent signal. The signal converter includes a reference voltage generator, a plurality of four-input differential comparators, timing recovery circuitry, and signal conversion circuitry. The reference voltage generator is operative to generate a plurality of progressively larger differential reference voltages. The plurality of differential comparators are each operative to compare magnitude of a differential input voltage with magnitude of a dedicated one of the progressively larger differential reference voltages and produce a differential output voltage having a first logical sense if the magnitude of the differential input voltage is greater than the magnitude of the differential reference voltage, and having a second logical sense if the magnitude of the differential input voltage is less than the magnitude of the differential reference voltage. Each comparator has an offset input voltage. The timing recovery circuitry is configured to receive the differential output voltages from each of the differential comparators and is operative to derive a clock via edge detection and generate a recovered clock signal. The signal conversion circuitry is coupled with the timing recovery circuitry and the differential comparators and is operative to convert the differential output voltages into a binary equivalent. A method is also provided.

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Dc Sessions