Cirrus Logic Inc.

National Semiconductor Corporation

Dayakar C Reddy

Suhas S Patil

Chester F Bassetti, Jr

Modugu V Reddy

Mahmud M Assar

Bryan Michael Richter

Sriram Ramamurthy

Ekaputra Laiman

H Ravindra

Ernest S Lin

Krishnan C Dharmarajan

Chester Floyd Bassetti, Jr

A video controller for controlling at least two video displays incorporates a video memory for storing first and second video frames of interleaved pixel data. A video memory controller connected to the video memory sequentially reads data for a first pixel from the first video frame and data for a second pixel from the second video frame. Each pixel data is in turn transferred to a look-up table connected to the video memory controller which converts the first and second pixel data to first and second display data. A selector coupled to the look-up table alternately routes the first display data to one video display and routes the second display data to the other video display.

Dual display video controller

An image displayed on a digital display such as a flat panel display is rotated while the same image is displayed on a cathode ray tube display in unrotated form. When image rotation is selected, the read address sequence into a frame buffer may be reversed and the bit read sequence may be reversed. Thus a frame of panel pixel data stored within the frame buffer of an external video memory may be scanned onto a flat panel to display a rotated image.

Image rotation for video displays

A technique for modulating pixels of a display panel for forming an image. Each pixel has an associated pixel frame, which is a period of time during which the pixel is modulated to achieve an appropriate greyscale level for the pixel. Each pixel frame includes a plurality of sub-frames. During each of the sub-frames, the pixel is placed in 'on' condition or in an 'off' condition according to a selected one of a plurality of predetermined greyscale sequences. Each greyscale sequence corresponds to a greyscale level for the pixel frame. A display frame is formed when each pixel in the display is appropriately modulated according to an image to be displayed. The displayed image is continually updated by displaying a sequence of display frames. The display panel is divided into blocks of sixteen pixels arranged in a four-by-four array. The greyscale sequences for pixels in a block are offset from one another by various numbers of sub-frames. This offset is termed pixel dispersion. The pixel blocks are grouped in four-by-four arrays of sixteen pixel blocks. Greyscale sequences for modulating the pixels in a block are offset from sequences for pixels in other blocks in the array by various numbers of sub-frames. This offset is termed block dispersion. Multiple arrays of blocks are updated in an identical manner to form a complete display panel.

Dispersion-based technique for modulating pixels of a digital display panel

A display system in a computer or multimedia system maintains a predetermined image quality. The display system includes an intelligent display driver controller (IDDC), a serial PROM, display screen, and sensors. The IDDC controls display of input image data on the display screen based on a control set. The serial PROM stores a plurality of such control sets, each of which has a predetermined effect on the image quality. The sensor measures a parameter, a change in which may degrade the image quality on the display screen. In response to such a change, the IDDC retrieves a new control set from the serial PROM, and controls display of input image data based on the new control set retrieved. As a result, the IDDC maintains the predetermined image quality on the display system independent of change in the measured parameter.

Method and apparatus for automatically maintaining a predetermined image

A technique for performing spacial dithering for a digital display system. A display panel is portioned into eight-by-eight arrays of 64 pixels, each pixel including three primary color sub-pixels. A predetermined number of bits represent a color level for each sub-pixel according to image data. If the display system can accept only fewer bits than the predetermined number, bits must be discarded. The discarded bits are used to modify the remaining bits before the remaining bits are passed to the display system. A memory stores 64 tables, each table including an entry for each pixel within an eight-by-eight array. The entry for a pixel determines whether or not the color level for the corresponding sub-pixel is to be decremented by one. A first of the sixty-four tables does not result in decrementing any color levels. Each successive table decrements the color level for one more pixel than the previous table. The values of discarded bits select among the stored tables. whereas, the values of bits that are retained are selectively decremented according to entries in the selected table. Entries in the tables are dispersed so as to avoid decrementing color levels in a pattern that would otherwise tend to result in image artifacts. This is accomplished by avoiding vertical, horizontal or diagonal lines, and checker-board patterns of pixels for which the color level is decremented. As a result, artifacts induced by the dithering process are reduced in comparison to prior dithering techniques.

Dispersion-based technique for performing spacial dithering for a

A digital system provides command data to a display system during the display time period such that minimal image degradation occurs. The digital system includes a CPU coupled to a graphics controller coupled to a display system via a cable. The display system includes an intelligent display driver controller (IDDC), driver circuits, display screen, and possibly sensors. The IDDC operates on image data and instructs the driver circuits to display an image on the display screen. Operating condition changes measured by transducers may result in a degradation in image quality unless a response is made. The digital system may automatically respond to operating condition changes to maintain a predetermined image quality level. Alternatively a user's request may change the image quality. In either case the CPU is interrupted and it provides one or more control sets of command data interspersed within the image data transparently to the graphics controller. The IDDC receives one or more control sets from the graphics controller and may store a control set to adjust the control over the driver circuits thereby preserving the image quality. Changes to hardware and software are minimized to reduce the costs of adding these improvements.

The system provides for vertical or horizontal centering, or both, without the use of a memory frame buffer, of raster image data whose start time and duration cannot be controlled. The centering is accomplished by controlling the frame start time and line start time of the overall display of the raster imaging surface. This is accomplished in the case of vertical centering by detecting the time of the beginning of the first or last line, or both, of the total lines of the raster image data to be displayed an controlling the start time of a subsequent one of the frames based on that detected time. Horizontal centering is carried out by detecting the time of the beginning of the first or last column, or both, of the columns in one or more of the lines of the raster image data and controlling the start time of subsequent ones of the lines based on that detected time.

System for raster imaging with automatic centering and image compression

The perception of grayscale shading on a digitally commanded display is produced by commanding pixels of the display with brightness-setting signals of differing average duty cycles. Brightness-setting signals having one brightness level associated with them are phase shifted in relation to time and distributed to spaced apart pixel locations at which the one brightness level is to be produced. The energization of spatially adjacent pixels is scattered in time and pixels which are energized at the same time are selected to be spatially scattered so as to avoid the perception of visual disturbances such as flickering and surface streaming.

Method and apparatus for producing perception of high quality grayscale

The system provides for vertical or horizontal centering, or both, without the use of a memory frame buffer, of raster image data whose start time and duration cannot be controlled. The centering is accomplished by controlling the frame start time and line start time of the overall display of the raster imaging surface. This is accomplished in the case of vertical centering by detecting the time of the beginning of the first or last line, or both, of the total lines of the raster image data to be displayed and controlling the start time of a subsequent one of the frames based on that detected time. Horizontal centering is carried out by detecting the time of the beginning of the first or last column, or both, of the columns in one or more of the lines of the raster image data and controlling the start time of subsequent ones of the lines based on that detected time.

Disclosed is a set of functional components (tiles), consisting in part of subgate elements, which, by their design, facilitate the creation of dense integrated circuits, without forfeiting the capability of modifying the functionality of individual tiles by late mask programming techniques. Overall densities approaching those obtained with hand-crafted, custom designs can be obtained in part because such components are designed to be tiled throughout a storage logic array, permitting the creation of orthogonal logic gates as well as individual gates (and more complex functions) the functionality of which is distributed horizontally, vertically and even in a zigzag fashion. Moreover, the transition time from prototype to high volume manufacturing is reduced significantly due to the ease with which even complex functions can be repaired and enhanced.

Programmable tiles

Disclosed is a set of functional components (tiles), consisting in part of subgate elements, which, by their design, facilitate the creation of dense integrated circuits, without forfeiting the capability of modifying the functionality of individual tiles by late mask programming techniques. Overall densities approach those obtained with hand-crafted, custom designs can be obtained in part because such components are designed to be tiled throughout a storage logic array, permitting the creation of orthogonal logic gates as well as individual gates (and more complex functions) the functionality of which is distributed horizontally, vertically and even in a zigzag fashion. Moreover, the transition time from prototype to high volume manufacturing is reduced significantly due to the ease with which even complex functions can be repaired and enhanced.

Growing community of inventors

San Jose, CA, United States of America

Dayakar C Reddy