Intel Corporation

Dawson L Yee

Thomas A Rampone

Edward L Solari

Earl Roger Noar

A method and apparatus for a connection system to a substrate is provided. The system includes a substrate having a mounting hole to permit an object to be coupled to the substrate. The substrate further includes a conductive pattern around the mounting hole on the substrate. The conductive pattern is designed to contact an interface, and selectively couple a ground signal to the object coupled to the substrate.

Flexible connection system

A printed circuit board (PCB) includes a plurality of electronic devices electrically coupled together and disposed on a first side of the PCB. The PCB also includes a rail that is connected to the underside of the PCB. This rail is configured to cooperatively engage a rail guide connected to the chassis of the computer system such that the rail guide holds the rail and the PCB to the chassis, and the PCB and rail can slide with respect to the chassis.

Method and apparatus for attaching a printed circuit board to a chassis

Under one aspect of the invention, the invention includes a multilayered substrate. The substrate includes a primary side having a first group of connection points, including a first connection point, having a first layout to interface with a first chip. The substrate also includes a secondary side having a second group of connection points, including a second connection point, having a layout identical to the first layout, to interface with a second chip. The substrate also includes an intermediate connection point coupled to the first and second connection points through first and second branch traces each having substantially the same electrical length.

Routing topology for identical connector point layouts on primary and

An interconnection between a cartridge and ground is described. The apparatus includes a cartridge and a shielding electrically coupled to the cartridge. The shielding is designed to electrically couple the cartridge to the substrate when the cartridge is attached to the substrate.

Electro-magnetic interference shielding

A printed circuit board which has a layer of electrically resistive material that can provide a pull-up/pull-down resistor for the board. The printed circuit board includes a substrate which has a conductive plane located on the top surface of the board. The conductive plane is typically dedicated to electrical power. The board also has a via that is connected to an internal signal line. The resistive material is applied to the top surface to connect the conductive plane to the via and the signal line. The resistive material can be applied with a screening process which simplifies the assembly process of the resistor. Additionally, the resistive material is relatively small and located adjacent to the via so that the resistor does not occupy valuable board space.

Built in board resistors

A computer system including a chassis having a number of PCB support structures affixed thereon is disclosed. The PCB support structures are configured to support a PCB of one of a number of pre-determined lengths, employing one of a number of subset combinations of the PCB support structures. However, a constant predefined total number of fasteners is employed regardless of the length of the PCB.

Computer system with a chassis equipped with support structures

An apparatus is provided for controlling a memory refresh operation in a computer system having a processor coupled to a host volatile memory via a memory controller, a system bus controller coupled to the processor via the memory controller, and a plurality of devices coupled to the system bus controller via a system bus. The apparatus includes a first timer coupled to the memory controller for generating a first memory refresh signal at a first predetermined time interval to cause the memory controller to perform the memory refresh operation on the host volatile memory. A second timer is coupled to the system bus controller for generating a second memory refresh signal at a selective time interval to causes the system bus controller to perform the memory refresh operation on the plurality of devices. A program is provided for detecting the refresh requirement of the plurality of devices in order to determine the selective time interval. When the program detects that one of the plurality of devices requires the memory refresh operation, the program sets the selective time interval to a second predetermined time interval. When the program detects that none of the plurality of devices requires the memory refresh operation, the program switches off the second timer. A method of controlling the memory refresh operation is also described.

Variable refresh intervals for system devices including setting the

A computer system has a dynamically adjustable speed bus. The dynamic speed bus system decreases the length of the bus cycle accesses required for fast peripherals; but, maintains normal (longer) length bus cycles for slower peripherals. Circuitry is provided to decrease the bus cycle length by increasing the clock frequency to the bus controller which controls the bus. When accessing peripherals that can support only normal length bus cycles, the circuitry of the present invention drives the bus controller with the normal lower clock frequency. When accessing faster peripherals, a higher clock frequency is generated such that the waveform transitions smoothly between the low and high bus frequencies. The dynamic speed bus circuitry of the present invention is divided into two logic sections: 1) a decode section and 2) a clock generation section. The decode section identifies faster peripherals that are compatible with shorter bus cycles.

Apparatus using a state machine for generating selectable clock

A bus driver circuit having an active low-side driver and a hybrid high-side driver. When driving a logic high, the bus driver circuit delivers an active 'kick' to pull the bus to a logic high state quickly and then releases the bus, allowing a weak pull-up resistor to maintain the voltage level of the bus for the remainder of the valid data phase. This kick is of limited duration, preferably lasting only long enough to bias the bus to a stable logic high while providing a remaining portion of the valid data phase that is of sufficient length for a contending bus agent to pull the bus low. The weak pull-up resistor is of sufficient size to reduce the chance that several resistors in parallel will prevent any active low-side driver of any bus agent from pulling the bus down to a low state.

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Beaverton, OR, United States of America

Dawson L Yee