Samsung Electronics Co., Ltd.

Seoul National University

Dawoon Choi

Seungjin Lee

Myungsoo Noh

Hee Jae Jeong

Noyoung Chung

Sunghun Jung

Jooho Kim

Yunhyoung Nam

Kyoil Koo

Donyun Kim

Inseop Lee

Yunkyoung Song

Bongkeun Kim

Provided is a layout design method including designing a preliminary layout including a source/drain contact pattern of an integrated circuit device, designing a first layout including a cut pattern for cutting the source/drain contact pattern, designing a second layout configured by excluding a pattern overlapping the pattern of the first layout from the preliminary layout, and correcting the preliminary layout by reflecting an etch skew based on at least one parameter of the second layout.

Layout design method and method of manufacturing integrated circuit device using the same

An integrated circuit (IC) device includes a fin-type active region extending in a first lateral direction on a device region of a substrate. A gate line extends in a second lateral direction on the fin-type active region. The second lateral direction intersects with the first lateral direction. A source/drain region is adjacent to one side of the gate line on the fin-type active region. A gate contact is on the gate line and connected to the gate line. A source/drain contact is on the source/drain region and includes a first segment facing the gate contact and a second segment integrally connected to the first segment. The second segment extends from the first segment in the second lateral direction. In the first lateral direction, a first distance from the first segment to the gate line is greater than a second distance from the second segment to the gate line.

Integrated circuit device

A method for detecting a stochastic weak point of a layout pattern of a semiconductor integrated circuit includes: forming a semiconductor integrated circuit by exposing a wafer which is masked by a layout pattern and coated with a photoresist to light, and etching the circuit according to the layout pattern, calculating line edge roughness (LER) of the circuit, and calculating a variability constant for fitting the line edge roughness to a normal distribution from a polymer concentration value of the photoresist. The polymer concentration value is calculated from modeling the layout pattern, a total value of intensity of light reaching the photoresist, and an intensity value of light reaching one point of the photoresist. The method further includes calculating a probability distribution of the polymer concentration value of the layout pattern based on the variability constant, and calculating a stochastic weak point of the layout pattern from the probability distribution.

Method for detecting stochastic weak points of layout pattern of semiconductor integrated circuit and computer system performing the same

A method of measuring a critical dimension (CD) includes forming a plurality of patterns in a substrate, creating first to n-th images, where n is a natural number greater than 1, for first to n-th areas in the substrate, respectively, where the first to n-th areas do not overlap with each other, where each of the first to n-th areas comprising at least some of the plurality of patterns, creating a merged image for the first to n-th images, and measuring a CD for a measurement object from the plurality of patterns using the merged image. The merged image has a higher resolution than each of the first to n-th images.

Method for measuring CD using scanning electron microscope

Growing community of inventors

Hwaseong-Si, South Korea

Dawoon Choi