Advanced Micro Devices Corporation

Spansion Llc.

Other

Fasl LLC

Dawn M Hopper

Minh Van Ngo

Lu You

Richard J Huang

Fei Wang

Angela Tai Hui

David Keating Foote

Robert A Huertas

Kouros Ghandehari

Bharath Rangarajan

Mark T Ramsbey

Suzette Keefe Pangrle

Wenmei Li

Ramkumar Subramanian

Arvind Halliyal

Mark S Chang

Tazrien Kamal

Jack F Thomas

Tyagamohan Gottipati

Bhanwar Singh

Calvin T Gabriel

Hidehiko Shiraiwa

Lynne A Okada

Rinji Sugino

Stephen Keetai Park

Jeremy Isaac Martin

Pei-Yuan Gao

Carmen L Morales

John Caffall

Christof Streck

Scott Allan Bell

Tuan Duc Pham

Jeffrey Allan Shields

Kuo-Tung Chang

Hiroyuki Kinoshita

Cyrus E Tabery

John JianShi Wang

Ning Cheng

Unsoon Kim

Jean Y Yang

Yider Wu

Clifford Alan Zitlaw

Krishnashree Achuthan

Hieu T Pham

Qamrul Hasan

Guarionex Morales

John G Pellerin

Jacques J Bertrand

Atul Gupta

Joffre F Bernard

Jeff P Erhardt

Christy M-c Woo

Terri Jo Kitson

Clarence B Ferguson

Kelwin King Wai Ko

Stephan Keetai Park

Disclosed herein are system, method and/or computer program product embodiments for increasing memory bandwidth when accessing a plurality of memory devices. An embodiment operates by executing, by at least one processor, a first read operation to read data from a first memory device following an access time for the first memory device. The embodiment further includes executing, by the at least one processor, a second read operation to read data from a second memory device following an access time for the second memory device. The access time for the second memory device is substantially the same or longer than the access time for the first memory device plus a time it takes to read data from the first memory device.

Programmable latency count to achieve higher memory bandwidth

The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region widths are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.

Integrated circuit with contact region and multiple etch stop insulation layer

Semiconductor formation method that utilizes multiple etch stop layers

The present invention is a semiconductor contact formation system and methods that form contact insulation regions comprising multiple etch stop sublayers that facilitate formation of contacts. This contract formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop contact formation process in which a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region width are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.

Semiconductor contact and nitride spacer formation system and method

A manufacturing method for a dual bit flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer with the depositing performed without using ammonia at an ultra-slow deposition rate. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, high-density data retention liner to reduce charge loss, covers the wordline and the charge-trapping dielectric layer. An interlayer dielectric layer is deposited over the data retention liner.

Semiconductor memory with data retention liner

A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell including a charge trapping dielectric charge storage layer in a semiconductor device; and during processing steps subsequent to formation of the charge trapping dielectric charge storage layer, protecting the charge trapping dielectric flash memory cell from exposure to a level of UV radiation sufficient to deposit a non-erasable charge in the charge trapping dielectric flash memory cell. In one embodiment, the step of protecting is carried out by selecting processes in BEOL fabrication which do not include use, generation or exposure of the semiconductor device to a level of UV radiation sufficient to deposit the non-erasable charge.

Protection of charge trapping dielectric flash memory devices from UV-induced charging in BEOL processing

Semiconductor devices comprising interconnect with improved adhesion of barrier layers to dielectric layers are formed by laser thermal annealing exposed surfaces of a dielectric layer in an atmosphere of NHand N, and subsequently depositing Ta to form a composite barrier layer. Embodiments include forming a dual damascene opening in an interlayer dielectric comprising F-containing silicon oxide, such as F-containing silicon oxide derived from F-TEOS, laser thermal annealing the exposed silicon oxide surface in NHand N, depositing Ta and then filling the opening with Cu. Laser thermal annealing in NHand Ndepletes the exposed silicon oxide surface of F while forming an N-rich surface region. Deposited Ta reacts with the Nin the N-rich surface region to form a composite barrier layer comprising a graded layer of tantalum nitride and a layer of &#x3b1;-Ta thereon.

Interconnects with improved barrier layer adhesion

A structure and method for reducing standing waves in a photoresist during manufacturing of a semiconductor is presented. Embodiments of the present invention include a method for reducing standing wave formation in a photoresist during manufacturing a semiconductor device comprising depositing a first anti-reflective coating having an extinction coefficient above a material, and depositing a second anti-reflective coating having an extinction coefficient above the first anti-reflective coating, such that the first anti-reflective coating and the second anti-reflective coating reduce the formation of standing waves in a photoresist during a lithography process.

Structure and method for reducing standing waves in a photoresist

According to one exemplary embodiment, a method for forming a contact over a silicide layer situated in a semiconductor die comprises a step of depositing a barrier layer on sidewalls of a contact hole and on a native oxide layer situated at a bottom of the contact hole, where the sidewalls are defined by the contact hole in a dielectric layer. The step of depositing the barrier layer on the sidewalls of the contact hole and on the native oxide layer can be optimized such that the barrier layer has a greater thickness at a top of the contact hole than a thickness at the bottom of the contact hole. According to this exemplary embodiment, the method further comprises a step of removing a portion of the barrier layer and the native oxide layer situated at the bottom of the contact hole to expose the silicide layer.

Method for preventing an increase in contact hole width during contact formation

A method of preventing UV charging of flash NVROM cells during fabrication and a device thereby formed. During device fabrication, a UV blocking layer is deposited over the floating gates. The UV blocking layer substantially blocks UV from entering the gate regions so as to prevent electron mobility sufficient to render the cells unprogrammable or unerasable. The reduced electron migration during processing of the NVROM leads to increased yield and reliability of the devices.

Flash NVROM devices with UV charge immunity

Oxide voiding is eliminated was substantially reduced by laser thermal annealing. Embodiments include fabricating flash memory devices by depositing a BPSG over spaced apart transistors as the first interlayer dielectric with voids formed in gaps between the transistors and laser thermal annealing the BPSG layer in flowing nitrogen to eliminate or substantially reduce the voids by reflowing the BPSG layer.

Laser thermal annealing to eliminate oxide voiding

A method of manufacturing a semiconductor. A conventional bottom anti-reflective coating is applied over a reflective surface, for example an inter-layer dielectric. A second anti-reflective coating is deposited over the first anti-reflective coating. The second anti-reflective coating is organic and may be deposited through a spin-on process. The organic anti-reflective coating may be deposited with more exacting optical properties and better control of the layer thickness than conventional bottom anti-reflective coatings applied via chemical vapor deposition processes. The combination of the two layers of anti-reflective materials, the materials having differing optical properties, demonstrates superior control of reflections from underlying materials compared with conventional art methods. More particularly, an organic anti-reflective coating in conjunction with an inorganic anti-reflective coating may cancel reflections across a wide range of thicknesses in an underlying dielectric layer. The superior anti-reflective structure of embodiments of the present invention allow patterning of semiconductor structures at smaller critical dimensions with greater accuracy, rendering competitive advantages in device speed, density and cost.

Organic spin-on anti-reflective coating over inorganic anti-reflective coating

Device leakage due to spacer undercutting is remedied by depositing a B-doped HDP or a BP-doped HDP oxide gap filling layer capable of flowing into undercut regions. Embodiments include depositing a B or BP-doped HDP oxide film containing 4 to 6 wt. % B over closely spaced apart non-volatile transistors and heating during and subsequent to deposition to complete flowing of the B- or BP-HDP oxide into and filling the undercut regions on the sidewall spacers and to densify the B- or BP-HDP oxide.

Reflowable-doped HDP film

A method for filling an isolation trench structure during a semiconductor fabrication process is disclosed. The method includes a two-step deposition process that includes depositing a silicon-rich liner on the trench surface, and thereafter, filling the isolation trenches with an oxide utilizing a biased high density plasma deposition process. In a preferred embodiment, the silicon-rich liner is an in-situ HDP liner having a thickness of between 100 and 400 Angstroms, and preferably 200 Angstroms. Depositing a silicon-rich liner on the trench surface prior to depositing the high density plasma oxide eliminates the formation of defects at the surface of the isolation trench structure. Thus, the quality of the oxide fill is improved, as is yield and device performance.

Isolation trench fill process

A manufacturing method for an integrated circuit memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, ultra-violet block data retention liner covers the wordline and the charge-trapping dielectric layer. The reduced hydrogen levels reduce the charge loss compared to prior art. The surface of the liner is processed to block UV light before completing the integrated circuit.

Liner for semiconductor memories and manufacturing method therefor

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San Jose, CA, United States of America

Dawn M Hopper